Apache NiFi 1.5/1.6/1.9.2+ Processor to produce DDL

Apache NiFi 1.10 DJL

GTFS / ProtoBuf Data

This is A NiFi processor Created to Stream the contents of a FlowFile to Ignite Cache.

A custom processor implemented in Verilog HDL for image down sampling for UOM's EN3030 Circuits and Systems Design module ❄

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

A new EPU, completely virtual, in the browser

Custom nifi kinesis get processor

This project is a custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. It demonstrates core CPU concepts and is ideal for learning about pipelined processor design and simulation.

An assembler for the SPU using rust