issues Search Results · repo:thedatabusdotio/fpga-ml-accelerator language:Verilog
Filter by
4 results
(71 ms)4 results
inthedatabusdotio/fpga-ml-accelerator (press backspace or delete to remove)Hi Batman ,
Thanks a lot for the amazing tutorial you provide on your website.
I wanted to know if it was possible to use your code? As there is no license provided, copyright law applies by default. ...
MaxenceBouvier
- Opened on May 23, 2024
- #4
If you try to input one of the inputs (say a) = 0, and then for example b = -1.42 (so a negative number)
the result instead of being 0, will have the MSB flipped to one.
to fix this:
assign q_result[N-1] ...
0dayboi
- Opened on Aug 1, 2023
- #3
If the ce signal is set to 1 on the posedge clk, the valid_op signal of the simulation output is wrong,Pooling model seems not well work。
chenpaopao
- Opened on May 9, 2022
- #1

Learn how you can use GitHub Issues to plan and track your work.
Save views for sprints, backlogs, teams, or releases. Rank, sort, and filter issues to suit the occasion. The possibilities are endless.Learn more about GitHub IssuesProTip!
Restrict your search to the title by using the in:title qualifier.
Learn how you can use GitHub Issues to plan and track your work.
Save views for sprints, backlogs, teams, or releases. Rank, sort, and filter issues to suit the occasion. The possibilities are endless.Learn more about GitHub IssuesProTip!
Restrict your search to the title by using the in:title qualifier.