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AUC Open Source Hardware Lab

Projects by the Open Source Hardware Lab at the American University in Cairo (AUC).

57 followers
https://www1.aucegypt.edu/faculty/cse/mshalan/auc_oshw_lab.html

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Fault Fault Public

A complete open-source design-for-testing (DFT) Solution

Swift 160 32
DFFRAM DFFRAM Public

Standard Cell Library based Memory Compiler using FF/Latch cells

Verilog 148 33

Repositories

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Showing 10 of 27 repositories

Fault Public
A complete open-source design-for-testing (DFT) Solution

AUCOHL/Fault’s past year of commit activity

Swift 160 Apache-2.0 32 11 (1 issue needs help) 0 Updated May 28, 2025
Lighter Public
An automatic clock gating utility

AUCOHL/Lighter’s past year of commit activity

Verilog 49 Apache-2.0 5 3 0 Updated Apr 15, 2025
OpenLane Public Forked from efabless/openlane2
Premier open-source RTL-to-GDSII flow

AUCOHL/OpenLane’s past year of commit activity

Python 2 Apache-2.0 64 0 0 Updated Apr 14, 2025
openlane-step-unit-tests Public Forked from efabless/openlane2-step-unit-tests
Step-specific Unit Tests for OpenLane

AUCOHL/openlane-step-unit-tests’s past year of commit activity

Verilog 0 Apache-2.0 5 0 0 Updated Feb 26, 2025
frigate-os Public Forked from efabless/frigate-os

AUCOHL/frigate-os’s past year of commit activity

Verilog 0 Apache-2.0 11 0 0 Updated Feb 26, 2025
openlane-ci-designs Public Forked from efabless/openlane2-ci-designs
Continuous Integration Designs for OpenLane 2.0.0 or higher

AUCOHL/openlane-ci-designs’s past year of commit activity

Verilog 0 8 0 0 Updated Feb 23, 2025
DFFRAM Public
Standard Cell Library based Memory Compiler using FF/Latch cells

AUCOHL/DFFRAM’s past year of commit activity

Verilog 148 Apache-2.0 33 28 4 Updated Jun 15, 2024
RTL-Repo Public
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

AUCOHL/RTL-Repo’s past year of commit activity

Python 14 Apache-2.0 1 0 0 Updated Jun 5, 2024
Stdcells Public
The Standard Cell Libraries Used By The Cloud V Platform

AUCOHL/Stdcells’s past year of commit activity

Verilog 1 1 0 0 Updated Mar 17, 2023
sky130-builds Public archive
What it says on the tin

AUCOHL/sky130-builds’s past year of commit activity

Python 4 2 0 0 Updated Apr 26, 2022

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