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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 6.2k 748

  2. XiangShan-doc Public

    Documentation for XiangShan

    Markdown 408 138

  3. HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 78 37

  4. difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 139 75

  5. xs-env Public

    XiangShan Frontend Develop Environment

    Shell 54 54

  6. NEMU Public

    C 268 100

Repositories

Showing 10 of 73 repositories
  • CoupledL2 Public

    Open-source non-blocking L2 cache

    Scala 37 23 0 13 Updated Mar 20, 2025
  • Utility Public
    Scala 10 22 0 6 Updated Mar 20, 2025
  • XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 6,208 748 84 57 Updated Mar 20, 2025
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 139 MulanPSL-2.0 75 6 8 Updated Mar 20, 2025
  • ChiselAIA Public

    RISC-V AIA in Chisel

    Scala 4 MulanPSL-2.0 3 11 0 Updated Mar 20, 2025
  • rocket-chip Public Forked from chipsalliance/rocket-chip

    Rocket Chip Generator

    Scala 4 1,163 0 3 Updated Mar 20, 2025
  • GEM5 Public
    C++ 74 BSD-3-Clause 33 18 16 Updated Mar 20, 2025
  • tutorial Public

    XiangShan Tutorial Website

    Markdown 3 CC-BY-4.0 0 0 0 Updated Mar 20, 2025
  • HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 78 37 2 1 Updated Mar 20, 2025
  • LibCheckpoint Public
    C 3 1 0 6 Updated Mar 20, 2025

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