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signed dword float to and from conversions <code>fcvt.l.s</code>, <code>fcvt.s.l</code>, <code>fcvt.l.d</code>, <code>fcvt.d.l</code> perform unsigned conversions instead

Status: Open.

#33 In d0iasm/rvemu;

· lenawanel opened on May 29, 2024

mixed and non-standard single preciscion implementation

Status: Open.

#32 In d0iasm/rvemu;

· lenawanel opened on May 27, 2024

unnessacary <code>Vec::retain</code> when executing sc.d/w instruction

Status: Open.

#31 In d0iasm/rvemu;

· lenawanel opened on May 26, 2024

Networking not working with Ubuntu

Status: Open.

#29 In d0iasm/rvemu;

· Mylab6 opened on Nov 28, 2023

Support img files for Webassembly

Status: Open.

#28 In d0iasm/rvemu;

· Immortalin opened on Nov 3, 2023

Bus memory region ends off by one?

Status: Open.

#26 In d0iasm/rvemu;

· SamuelMcGowan opened on Jun 20, 2023

Single precision instruction on double precision register value

Status: Open.

#25 In d0iasm/rvemu;

· philippuk opened on Jun 3, 2023

Where can I get the test resource's source code?

Status: Open.

#24 In d0iasm/rvemu;

· sunmin89 opened on May 3, 2023

how to run your kernel using qemu

Status: Open.

#23 In d0iasm/rvemu;

· quantrpeter opened on Mar 27, 2023

I can't seem to run Linux

Status: Open.

#17 In d0iasm/rvemu;

· Penncilk opened on Dec 15, 2021

div instruction should not set fcsr/DZ when dividing by zero

Status: Open.

#16 In d0iasm/rvemu;

· FanShupei opened on Aug 31, 2021

WASM version hangs on OpenSBI payload firmware

Status: Open.

#15 In d0iasm/rvemu;

· repnop opened on May 12, 2021