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Intel® Compiler for SystemC* (ICSC) translates synthesizable SystemC design into equvivalent SystemVerilog code.
ICSC checks a SystemC design for common coding mistakes and generates human-readable SystemVerilog code. The tool supports SystemC synthesizable subset in method and thread processes, and arbitrary C++ code in module constructors. ICSC is based on Clang/LLVM 18.1.8 and includes SystemC 3.0.0.
See more information at Intel Compiler for SystemC wiki.
Single Source library consists of communication channels including Target/Initiator, FIFO, Pipe, Buffer, Register and others. The channels have functional interfaces similar to TLM 1.0.
There are Single Source training slides.
See more information at Single Source library.
ICSC is based on Clang/LLVM frontend and can be installed at most Linux OS. There is install.sh script that downloads and builds ICSC and the required dependencies at SLES15, SLES12, Ubuntu 22.04, and Ubuntu 20.04.
An instruction how to install and run ISCS is given at Getting started.
User guide document describes installation procedure, run tool options, preparation of SystemC design for synthesis, tool extensions and advanced verification features.
ICSC supports SystemC Synthesizable Subset. Details of SystemC/C++ subset supported are described at SystemC/C++ supported.
- Single Source library for high-level modelling and hardware synthesis, at DvCon Europe 2024
- Intel Compiler for SystemC and SystemC common library at CHIPS tech summit 2022
- Temporal assertions in SystemC at DvCon'2020 and SystemC evolution day'2020
- SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC at DvCon'2019
ICSC is distributed under the Apache License v2.0 with LLVM Exceptions.
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