method_clock_sensitive.sv

//==============================================================================
//
// The code is generated by Intel Compiler for SystemC, version 1.6.2
// see more information at https://github.com/intel/systemc-compiler
//
//==============================================================================

//==============================================================================
//
// Module: A ()
//
module A // "a"
(
    input logic clk,
    input logic nrst
);

// Variables generated for SystemC signals
logic signed [31:0] c;

//------------------------------------------------------------------------------
// Clocked THREAD: thrdProc (test_clock_sensitive.cpp:42:5) 

// Thread-local variables
logic signed [31:0] c_next;

// Next-state combinational logic
always_comb begin : thrdProc_comb     // test_clock_sensitive.cpp:42:5
    thrdProc_func;
end
function void thrdProc_func;
    c_next = c;
    c_next = c + 1;
endfunction

// Synchronous register update
always_ff @(posedge clk or negedge nrst) 
begin : thrdProc_ff
    if ( ~nrst ) begin
        c <= 0;
    end
    else begin
        c <= c_next;
    end
end

endmodule