misc_cross_hierarchy_bind_vector.sv

//==============================================================================
//
// The code is generated by Intel Compiler for SystemC, version 1.6.14
// see more information at https://github.com/intel/systemc-compiler
//
//==============================================================================

//==============================================================================
//
// Module: Top ()
//
module Top // "top"
(
    input logic clk
);

// Variables generated for SystemC signals
logic nrst;
logic [11:0] s;
logic [11:0] sigs[2];

//------------------------------------------------------------------------------
// Method process: proc (test_cross_hierarchy_bind_vector.cpp:85:5) 

always_comb 
begin : proc     // test_cross_hierarchy_bind_vector.cpp:85:5
    sigs[0] = 0;
    sigs[1] = s;
end


//------------------------------------------------------------------------------
// Child module instances

B mod_b
(
  .clk(clk),
  .nrst(nrst),
  .ains(sigs)
);

endmodule



//==============================================================================
//
// Module: B (test_cross_hierarchy_bind_vector.cpp:73:5)
//
module B // "top.mod_b"
(
    input logic clk,
    input logic nrst,
    input logic [11:0] ains[2]
);

// Variables generated for SystemC signals
logic [11:0] s;
logic [11:0] bins_v[2];

//------------------------------------------------------------------------------
// Clocked THREAD: threadProc (test_cross_hierarchy_bind_vector.cpp:52:5) 

// Thread-local variables
logic [31:0] cntr;
logic [31:0] cntr_next;
logic [11:0] s_next;

// Next-state combinational logic
always_comb begin : threadProc_comb     // test_cross_hierarchy_bind_vector.cpp:52:5
    threadProc_func;
end
function void threadProc_func;
    cntr_next = cntr;
    s_next = s;
    cntr_next = cntr_next + (bins_v[0] + bins_v[1]);
    s_next = cntr_next;
endfunction

// Synchronous register update
always_ff @(posedge clk or negedge nrst) 
begin : threadProc_ff
    if ( ~nrst ) begin
        cntr <= 0;
    end
    else begin
        cntr <= cntr_next;
        s <= s_next;
    end
end


//------------------------------------------------------------------------------
// Child module instances

A mod_a
(
  .asigs_s(bins_v),
  .clk(clk),
  .nrst(nrst),
  .ains(ains)
);

endmodule



//==============================================================================
//
// Module: A (test_cross_hierarchy_bind_vector.cpp:40:5)
//
module A // "top.mod_b.mod_a"
(
    output logic [11:0] asigs_s[2],
    input logic clk,
    input logic nrst,
    input logic [11:0] ains[2]
);

// Variables generated for SystemC signals
logic [11:0] asigs[2];

// Assignments generated for C++ channel arrays
assign asigs_s = asigs;

//------------------------------------------------------------------------------
// Method process: proc (test_cross_hierarchy_bind_vector.cpp:26:5) 

always_comb 
begin : proc     // test_cross_hierarchy_bind_vector.cpp:26:5
    asigs[0] = ains[0];
    asigs[1] = ains[1];
end

endmodule