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[AArch64][SVE] Remove index_vector node.
Since index_vector is lowered into step_vector in D100816, we can just remove index_vector, use step_vector for codegen directly. Differential Revision: https://reviews.llvm.org/D101593
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -15360,19 +15360,6 @@ static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
1536015360
DAG.getConstant(MinOffset, DL, MVT::i64));
1536115361
}
1536215362

15363-
static SDValue performStepVectorCombine(SDNode *N,
15364-
TargetLowering::DAGCombinerInfo &DCI,
15365-
SelectionDAG &DAG) {
15366-
if (!DCI.isAfterLegalizeDAG())
15367-
return SDValue();
15368-
15369-
SDLoc DL(N);
15370-
EVT VT = N->getValueType(0);
15371-
SDValue StepVal = N->getOperand(0);
15372-
SDValue Zero = DAG.getConstant(0, DL, StepVal.getValueType());
15373-
return DAG.getNode(AArch64ISD::INDEX_VECTOR, DL, VT, Zero, StepVal);
15374-
}
15375-
1537615363
// Turns the vector of indices into a vector of byte offstes by scaling Offset
1537715364
// by (BitWidth / 8).
1537815365
static SDValue getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset,
@@ -15956,8 +15943,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
1595615943
return performExtractVectorEltCombine(N, DAG);
1595715944
case ISD::VECREDUCE_ADD:
1595815945
return performVecReduceAddCombine(N, DCI.DAG, Subtarget);
15959-
case ISD::STEP_VECTOR:
15960-
return performStepVectorCombine(N, DCI, DAG);
1596115946
case ISD::INTRINSIC_VOID:
1596215947
case ISD::INTRINSIC_W_CHAIN:
1596315948
switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -259,10 +259,8 @@ def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
259259
def SDT_AArch64DUP_PRED : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 3>, SDTCisVec<1>, SDTCVecEltisVT<1,i1>]>;
260260
def AArch64dup_mt : SDNode<"AArch64ISD::DUP_MERGE_PASSTHRU", SDT_AArch64DUP_PRED>;
261261

262-
def SDT_IndexVector : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<2>]>;
263-
def index_vector : SDNode<"AArch64ISD::INDEX_VECTOR", SDT_IndexVector, []>;
264-
def index_vector_oneuse : PatFrag<(ops node:$base, node:$idx),
265-
(index_vector node:$base, node:$idx), [{
262+
def step_vector_oneuse : PatFrag<(ops node:$idx),
263+
(step_vector node:$idx), [{
266264
return N->hasOneUse();
267265
}]>;
268266

@@ -1370,10 +1368,10 @@ let Predicates = [HasSVE] in {
13701368
defm INCP_ZP : sve_int_count_v<0b10000, "incp">;
13711369
defm DECP_ZP : sve_int_count_v<0b10100, "decp">;
13721370

1373-
defm INDEX_RR : sve_int_index_rr<"index", index_vector, index_vector_oneuse, AArch64mul_p_oneuse>;
1374-
defm INDEX_IR : sve_int_index_ir<"index", index_vector, index_vector_oneuse, AArch64mul_p, AArch64mul_p_oneuse>;
1375-
defm INDEX_RI : sve_int_index_ri<"index", index_vector, index_vector_oneuse>;
1376-
defm INDEX_II : sve_int_index_ii<"index", index_vector, index_vector_oneuse>;
1371+
defm INDEX_RR : sve_int_index_rr<"index", step_vector, step_vector_oneuse, AArch64mul_p_oneuse>;
1372+
defm INDEX_IR : sve_int_index_ir<"index", step_vector, step_vector_oneuse, AArch64mul_p, AArch64mul_p_oneuse>;
1373+
defm INDEX_RI : sve_int_index_ri<"index", step_vector, step_vector_oneuse>;
1374+
defm INDEX_II : sve_int_index_ii<"index", step_vector, step_vector_oneuse>;
13771375

13781376
// Unpredicated shifts
13791377
defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr", AArch64asr_p>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 52 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -4800,23 +4800,23 @@ multiclass sve_int_index_ii<string asm, SDPatternOperator op, SDPatternOperator
48004800
def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
48014801
def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
48024802

4803-
def : Pat<(nxv16i8 (op simm5_8b:$imm5, simm5_8b:$imm5b)),
4803+
def : Pat<(nxv16i8 (op simm5_8b:$imm5b)),
4804+
(!cast<Instruction>(NAME # "_B") (i32 0), simm5_8b:$imm5b)>;
4805+
def : Pat<(nxv8i16 (op simm5_16b:$imm5b)),
4806+
(!cast<Instruction>(NAME # "_H") (i32 0), simm5_16b:$imm5b)>;
4807+
def : Pat<(nxv4i32 (op simm5_32b:$imm5b)),
4808+
(!cast<Instruction>(NAME # "_S") (i32 0), simm5_32b:$imm5b)>;
4809+
def : Pat<(nxv2i64 (op simm5_64b:$imm5b)),
4810+
(!cast<Instruction>(NAME # "_D") (i64 0), simm5_64b:$imm5b)>;
4811+
4812+
// add(step_vector(step), dup(X)) -> index(X, step).
4813+
def : Pat<(add (nxv16i8 (oneuseop simm5_8b:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
48044814
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, simm5_8b:$imm5b)>;
4805-
def : Pat<(nxv8i16 (op simm5_16b:$imm5, simm5_16b:$imm5b)),
4815+
def : Pat<(add (nxv8i16 (oneuseop simm5_16b:$imm5b)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
48064816
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, simm5_16b:$imm5b)>;
4807-
def : Pat<(nxv4i32 (op simm5_32b:$imm5, simm5_32b:$imm5b)),
4817+
def : Pat<(add (nxv4i32 (oneuseop simm5_32b:$imm5b)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
48084818
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, simm5_32b:$imm5b)>;
4809-
def : Pat<(nxv2i64 (op simm5_64b:$imm5, simm5_64b:$imm5b)),
4810-
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, simm5_64b:$imm5b)>;
4811-
4812-
// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
4813-
def : Pat<(add (nxv16i8 (oneuseop (i32 0), simm5_8b:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4814-
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, simm5_8b:$imm5b)>;
4815-
def : Pat<(add (nxv8i16 (oneuseop (i32 0), simm5_16b:$imm5b)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4816-
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, simm5_16b:$imm5b)>;
4817-
def : Pat<(add (nxv4i32 (oneuseop (i32 0), simm5_32b:$imm5b)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4818-
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, simm5_32b:$imm5b)>;
4819-
def : Pat<(add (nxv2i64 (oneuseop (i64 0), simm5_64b:$imm5b)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4819+
def : Pat<(add (nxv2i64 (oneuseop simm5_64b:$imm5b)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
48204820
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, simm5_64b:$imm5b)>;
48214821
}
48224822

@@ -4843,43 +4843,43 @@ multiclass sve_int_index_ir<string asm, SDPatternOperator op, SDPatternOperator
48434843
def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
48444844
def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
48454845

4846-
def : Pat<(nxv16i8 (op simm5_8b:$imm5, GPR32:$Rm)),
4847-
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
4848-
def : Pat<(nxv8i16 (op simm5_16b:$imm5, GPR32:$Rm)),
4849-
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
4850-
def : Pat<(nxv4i32 (op simm5_32b:$imm5, GPR32:$Rm)),
4851-
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
4852-
def : Pat<(nxv2i64 (op simm5_64b:$imm5, GPR64:$Rm)),
4853-
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
4846+
def : Pat<(nxv16i8 (op GPR32:$Rm)),
4847+
(!cast<Instruction>(NAME # "_B") (i32 0), GPR32:$Rm)>;
4848+
def : Pat<(nxv8i16 (op GPR32:$Rm)),
4849+
(!cast<Instruction>(NAME # "_H") (i32 0), GPR32:$Rm)>;
4850+
def : Pat<(nxv4i32 (op GPR32:$Rm)),
4851+
(!cast<Instruction>(NAME # "_S") (i32 0), GPR32:$Rm)>;
4852+
def : Pat<(nxv2i64 (op GPR64:$Rm)),
4853+
(!cast<Instruction>(NAME # "_D") (i64 0), GPR64:$Rm)>;
48544854

4855-
// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
4856-
def : Pat<(add (nxv16i8 (oneuseop (i32 0), GPR32:$Rm)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4855+
// add(step_vector(step), dup(X)) -> index(X, step).
4856+
def : Pat<(add (nxv16i8 (oneuseop GPR32:$Rm)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
48574857
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
4858-
def : Pat<(add (nxv8i16 (oneuseop (i32 0), GPR32:$Rm)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4858+
def : Pat<(add (nxv8i16 (oneuseop GPR32:$Rm)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
48594859
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
4860-
def : Pat<(add (nxv4i32 (oneuseop (i32 0), GPR32:$Rm)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4860+
def : Pat<(add (nxv4i32 (oneuseop GPR32:$Rm)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
48614861
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
4862-
def : Pat<(add (nxv2i64 (oneuseop (i64 0), GPR64:$Rm)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4862+
def : Pat<(add (nxv2i64 (oneuseop GPR64:$Rm)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
48634863
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
48644864

4865-
// mul(index_vector(0, 1), dup(Y)) -> index_vector(0, Y).
4866-
def : Pat<(mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 0), (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
4865+
// mul(step_vector(1), dup(Y)) -> index(0, Y).
4866+
def : Pat<(mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
48674867
(!cast<Instruction>(NAME # "_B") (i32 0), GPR32:$Rm)>;
4868-
def : Pat<(mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 0), (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
4868+
def : Pat<(mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
48694869
(!cast<Instruction>(NAME # "_H") (i32 0), GPR32:$Rm)>;
4870-
def : Pat<(mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 0), (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
4870+
def : Pat<(mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
48714871
(!cast<Instruction>(NAME # "_S") (i32 0), GPR32:$Rm)>;
4872-
def : Pat<(mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 0), (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
4872+
def : Pat<(mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
48734873
(!cast<Instruction>(NAME # "_D") (i64 0), GPR64:$Rm)>;
48744874

4875-
// add(mul(index_vector(0, 1), dup(Y), dup(X)) -> index_vector(X, Y).
4876-
def : Pat<(add (muloneuseop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 0), (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4875+
// add(mul(step_vector(1), dup(Y), dup(X)) -> index(X, Y).
4876+
def : Pat<(add (muloneuseop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
48774877
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
4878-
def : Pat<(add (muloneuseop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 0), (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4878+
def : Pat<(add (muloneuseop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
48794879
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
4880-
def : Pat<(add (muloneuseop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 0), (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4880+
def : Pat<(add (muloneuseop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
48814881
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
4882-
def : Pat<(add (muloneuseop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 0), (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4882+
def : Pat<(add (muloneuseop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
48834883
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
48844884
}
48854885

@@ -4906,23 +4906,14 @@ multiclass sve_int_index_ri<string asm, SDPatternOperator op, SDPatternOperator
49064906
def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
49074907
def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
49084908

4909-
def : Pat<(nxv16i8 (op GPR32:$Rm, simm5_8b:$imm5)),
4909+
// add(step_vector(step), dup(X)) -> index(X, step).
4910+
def : Pat<(add (nxv16i8 (oneuseop simm5_8b:$imm5)), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
49104911
(!cast<Instruction>(NAME # "_B") GPR32:$Rm, simm5_8b:$imm5)>;
4911-
def : Pat<(nxv8i16 (op GPR32:$Rm, simm5_16b:$imm5)),
4912+
def : Pat<(add (nxv8i16 (oneuseop simm5_16b:$imm5)), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
49124913
(!cast<Instruction>(NAME # "_H") GPR32:$Rm, simm5_16b:$imm5)>;
4913-
def : Pat<(nxv4i32 (op GPR32:$Rm, simm5_32b:$imm5)),
4914+
def : Pat<(add (nxv4i32 (oneuseop simm5_32b:$imm5)), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
49144915
(!cast<Instruction>(NAME # "_S") GPR32:$Rm, simm5_32b:$imm5)>;
4915-
def : Pat<(nxv2i64 (op GPR64:$Rm, simm5_64b:$imm5)),
4916-
(!cast<Instruction>(NAME # "_D") GPR64:$Rm, simm5_64b:$imm5)>;
4917-
4918-
// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
4919-
def : Pat<(add (nxv16i8 (oneuseop (i32 0), simm5_8b:$imm5)), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
4920-
(!cast<Instruction>(NAME # "_B") GPR32:$Rm, simm5_8b:$imm5)>;
4921-
def : Pat<(add (nxv8i16 (oneuseop (i32 0), simm5_16b:$imm5)), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
4922-
(!cast<Instruction>(NAME # "_H") GPR32:$Rm, simm5_16b:$imm5)>;
4923-
def : Pat<(add (nxv4i32 (oneuseop (i32 0), simm5_32b:$imm5)), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
4924-
(!cast<Instruction>(NAME # "_S") GPR32:$Rm, simm5_32b:$imm5)>;
4925-
def : Pat<(add (nxv2i64 (oneuseop (i64 0), simm5_64b:$imm5)), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
4916+
def : Pat<(add (nxv2i64 (oneuseop simm5_64b:$imm5)), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
49264917
(!cast<Instruction>(NAME # "_D") GPR64:$Rm, simm5_64b:$imm5)>;
49274918
}
49284919

@@ -4949,29 +4940,24 @@ multiclass sve_int_index_rr<string asm, SDPatternOperator op, SDPatternOperator
49494940
def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
49504941
def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
49514942

4952-
def : SVE_2_Op_Pat<nxv16i8, op, i32, i32, !cast<Instruction>(NAME # _B)>;
4953-
def : SVE_2_Op_Pat<nxv8i16, op, i32, i32, !cast<Instruction>(NAME # _H)>;
4954-
def : SVE_2_Op_Pat<nxv4i32, op, i32, i32, !cast<Instruction>(NAME # _S)>;
4955-
def : SVE_2_Op_Pat<nxv2i64, op, i64, i64, !cast<Instruction>(NAME # _D)>;
4956-
4957-
// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
4958-
def : Pat<(add (nxv16i8 (oneuseop (i32 0), GPR32:$Rm)), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
4943+
// add(step_vector(step), dup(X)) -> index(X, step).
4944+
def : Pat<(add (nxv16i8 (oneuseop GPR32:$Rm)), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
49594945
(!cast<Instruction>(NAME # "_B") GPR32:$Rn, GPR32:$Rm)>;
4960-
def : Pat<(add (nxv8i16 (oneuseop (i32 0), GPR32:$Rm)), (nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
4946+
def : Pat<(add (nxv8i16 (oneuseop GPR32:$Rm)), (nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
49614947
(!cast<Instruction>(NAME # "_H") GPR32:$Rn, GPR32:$Rm)>;
4962-
def : Pat<(add (nxv4i32 (oneuseop (i32 0), GPR32:$Rm)), (nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
4948+
def : Pat<(add (nxv4i32 (oneuseop GPR32:$Rm)), (nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
49634949
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, GPR32:$Rm)>;
4964-
def : Pat<(add (nxv2i64 (oneuseop (i64 0), GPR64:$Rm)), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
4950+
def : Pat<(add (nxv2i64 (oneuseop GPR64:$Rm)), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
49654951
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, GPR64:$Rm)>;
49664952

4967-
// add(mul(index_vector(0, 1), dup(Y), dup(X)) -> index_vector(X, Y).
4968-
def : Pat<(add (mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 0), (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
4953+
// add(mul(step_vector(1), dup(Y), dup(X)) -> index(X, Y).
4954+
def : Pat<(add (mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
49694955
(!cast<Instruction>(NAME # "_B") GPR32:$Rn, GPR32:$Rm)>;
4970-
def : Pat<(add (mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 0), (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),(nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
4956+
def : Pat<(add (mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),(nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
49714957
(!cast<Instruction>(NAME # "_H") GPR32:$Rn, GPR32:$Rm)>;
4972-
def : Pat<(add (mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 0), (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),(nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
4958+
def : Pat<(add (mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),(nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
49734959
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, GPR32:$Rm)>;
4974-
def : Pat<(add (mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 0), (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),(nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
4960+
def : Pat<(add (mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),(nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
49754961
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, GPR64:$Rm)>;
49764962
}
49774963

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