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Commits on Mar 13, 2023

• [SelectionDAG] Fix mismatched truncate when combine BUILD_VECTOR with EXTRACT_SUBVECTOR

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Commits on Mar 2, 2023

• [WebAssembly] Skip implied bitmask operation in LowerShift

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Commits on Feb 22, 2023

• [WebAssembly] Add more combine pattern for vector shift

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Commits on Feb 17, 2023

• [WebAssembly] Fix simd bit shift intrinsics codegen

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• [WebAssembly] Update wasm.c with update_cc_test_checks.py. NFC

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Commits on Apr 24, 2022

• [InlineCost] Set LastCallToStaticBonus in ML inlining models.

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Commits on Jan 5, 2022

• [TTI] Return invalid cost for scalable vector in getShuffleCost

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Commits on Nov 24, 2021

• Revert "[Taildup] Don't tail-duplicate loop header with multiple successors as its latches"

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• Revert "Revert "Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values."""""

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Commits on Nov 1, 2021

• [Taildup] Don't tail-duplicate loop header with multiple successors as its latches

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• [TailDup] Add testcase for interpreter switch loop, NFC.

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• Revert "Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values.""""

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Commits on Sep 27, 2021

• Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values."""

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Commits on Sep 9, 2021

• Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values.""

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Commits on Aug 27, 2021

• [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

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• [AArch64][SVE] Add API for conversion between SVE predicate pattern and element number. NFC

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• [AArch64][SVE] Use getPTrue uniformly.NFC.

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Commits on Aug 18, 2021

• [CVP] processSwitch: Remove default case when switch cover all possible values.

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• [NFC][CVP] Add one switch testcase

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Commits on Jul 29, 2021

• [NFC][InstSimplify] Use more intuitive variable names.

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Commits on Jul 28, 2021

• [InstSimplify] Simplify llvm.vscale when vscale_range attribute exists

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Commits on Jul 27, 2021

• [NFC][InstCombine] Fix typo

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Commits on Jul 22, 2021

• [AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversion

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Commits on Jul 1, 2021

• [clang][AArch64][SVE] Handle PRValue under VLAT <-> VLST cast

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• [AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.

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Commits on May 10, 2021

• [AArch64][SVE] Remove index_vector node.

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Commits on Apr 30, 2021

• [AArch64][SVE] Lower index_vector to step_vector

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Commits on Apr 22, 2021

• [DAGCombiner] Allow operand of step_vector to be negative.

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Commits on Apr 20, 2021

• [DAGCombiner] Support fold zero scalar vector.

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• [AArch64][SVE] Combine add and index_vector

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Commits on Apr 15, 2021

• [DAGCombiner] Fold step_vector with add/mul/shl

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Commits on Apr 2, 2021

• [NFC][SVE] update sve-intrinsics-int-arith.ll under update_llc_test_checks.py

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• [AArch64][SVE] Lowering sve.dot to DOT node

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• [NFC][SVE] Use SVE_4_Op_Imm_Pat for sve_intx_dot_by_indexed_elem

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Commits on Mar 30, 2021

• [NFC][SVE] Remove redundant pattern

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