[RISCV] Introduce RISCV::RVVBytesPerBlock to simplify code [nfc]

llvm/include/llvm/TargetParser/RISCVTargetParser.h

@@ -49,6 +49,7 @@ struct CPUInfo {
 
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
+static constexpr unsigned RVVBytesPerBlock = RVVBitsPerBlock / 8;
 
 void getFeaturesForCPU(StringRef CPU,
                        SmallVectorImpl<std::string> &EnabledFeatures,

llvm/lib/IR/Type.cpp

@@ -1009,7 +1009,7 @@ static TargetTypeInfo getTargetTypeInfo(const TargetExtType *Ty) {
     unsigned TotalNumElts =
         std::max(cast<ScalableVectorType>(Ty->getTypeParameter(0))
                      ->getMinNumElements(),
-                 RISCV::RVVBitsPerBlock / 8) *
+                 RISCV::RVVBytesPerBlock) *
         Ty->getIntParameter(0);
     return TargetTypeInfo(
         ScalableVectorType::get(Type::getInt8Ty(C), TotalNumElts),

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

@@ -526,7 +526,7 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV(
   // Get VLEN in TargetReg
   const RISCVInstrInfo *TII = STI.getInstrInfo();
   Register TargetReg = RISCV::X6;
-  uint32_t NumOfVReg = Amount / (RISCV::RVVBitsPerBlock / 8);
+  uint32_t NumOfVReg = Amount / RISCV::RVVBytesPerBlock;
   BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoReadVLENB), TargetReg)
       .setMIFlag(Flag);
   TII->mulImm(MF, MBB, MBBI, DL, TargetReg, NumOfVReg, Flag);
@@ -1544,11 +1544,11 @@ RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const {
     // ObjectSize in bytes.
     int64_t ObjectSize = MFI.getObjectSize(FI);
     auto ObjectAlign =
-        std::max(Align(RISCV::RVVBitsPerBlock / 8), MFI.getObjectAlign(FI));
+        std::max(Align(RISCV::RVVBytesPerBlock), MFI.getObjectAlign(FI));
     // If the data type is the fractional vector type, reserve one vector
     // register for it.
-    if (ObjectSize < (RISCV::RVVBitsPerBlock / 8))
-      ObjectSize = (RISCV::RVVBitsPerBlock / 8);
+    if (ObjectSize < RISCV::RVVBytesPerBlock)
+      ObjectSize = RISCV::RVVBytesPerBlock;
     Offset = alignTo(Offset + ObjectSize, ObjectAlign);
     MFI.setObjectOffset(FI, -Offset);
     // Update the maximum alignment of the RVV stack section

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -1633,7 +1633,7 @@ bool RISCVTargetLowering::shouldExpandGetVectorLength(EVT TripCountVT,
 
   // The maximum VF is for the smallest element width with LMUL=8.
   // VF must be a power of 2.
-  unsigned MaxVF = (RISCV::RVVBitsPerBlock / 8) * 8;
+  unsigned MaxVF = RISCV::RVVBytesPerBlock * 8;
   return VF > MaxVF || !isPowerOf2_32(VF);
 }
 
@@ -22713,7 +22713,7 @@ EVT RISCVTargetLowering::getOptimalMemOpType(const MemOp &Op,
 
   // If the minimum VLEN is less than RISCV::RVVBitsPerBlock we don't support
   // fixed vectors.
-  if (MinVLenInBytes <= RISCV::RVVBitsPerBlock / 8)
+  if (MinVLenInBytes <= RISCV::RVVBytesPerBlock)
     return MVT::Other;
 
   // Prefer i8 for non-zero memset as it allows us to avoid materializing

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -163,9 +163,8 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
     if (!MI.getOperand(1).isFI())
       return Register();
     FrameIndex = MI.getOperand(1).getIndex();
-    unsigned BytesPerBlock = RISCV::RVVBitsPerBlock / 8;
     unsigned LMUL = *getLMULForRVVWholeLoadStore(MI.getOpcode());
-    MemBytes = TypeSize::getScalable(BytesPerBlock * LMUL);
+    MemBytes = TypeSize::getScalable(RISCV::RVVBytesPerBlock * LMUL);
     return MI.getOperand(0).getReg();
   }
 
@@ -214,9 +213,8 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
     if (!MI.getOperand(1).isFI())
       return Register();
     FrameIndex = MI.getOperand(1).getIndex();
-    unsigned BytesPerBlock = RISCV::RVVBitsPerBlock / 8;
     unsigned LMUL = *getLMULForRVVWholeLoadStore(MI.getOpcode());
-    MemBytes = TypeSize::getScalable(BytesPerBlock * LMUL);
+    MemBytes = TypeSize::getScalable(RISCV::RVVBytesPerBlock * LMUL);
     return MI.getOperand(0).getReg();
   }
 

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -194,7 +194,7 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
     if (auto VLEN = ST.getRealVLen()) {
       // 1. Multiply the number of v-slots by the (constant) length of register
       const int64_t VLENB = *VLEN / 8;
-      assert(Offset.getScalable() % (RISCV::RVVBitsPerBlock / 8) == 0 &&
+      assert(Offset.getScalable() % RISCV::RVVBytesPerBlock == 0 &&
              "Reserve the stack by the multiple of one vector size.");
       const int64_t NumOfVReg = Offset.getScalable() / 8;
       const int64_t FixedOffset = NumOfVReg * VLENB;
@@ -221,11 +221,11 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
       ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
 
     assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
-    assert(ScalableValue % (RISCV::RVVBitsPerBlock / 8) == 0 &&
+    assert(ScalableValue % RISCV::RVVBytesPerBlock == 0 &&
            "Reserve the stack by the multiple of one vector size.");
-    assert(isInt<32>(ScalableValue / (RISCV::RVVBitsPerBlock / 8)) &&
+    assert(isInt<32>(ScalableValue / RISCV::RVVBytesPerBlock) &&
            "Expect the number of vector registers within 32-bits.");
-    uint32_t NumOfVReg = ScalableValue / (RISCV::RVVBitsPerBlock / 8);
+    uint32_t NumOfVReg = ScalableValue / RISCV::RVVBytesPerBlock;
     // Only use vsetvli rather than vlenb if adjusting in the prologue or
     // epilogue, otherwise it may disturb the VTYPE and VL status.
     bool IsPrologueOrEpilogue =