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mr-batmr-bat
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Trying to debug SRAM
1 parent 67c4297 commit 0172519

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7 files changed

+107
-85
lines changed

7 files changed

+107
-85
lines changed

‎Sec_8/EXE_Reg.v

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ module EXE_Stage_reg
33
(
44
clk,
55
rst,
6+
stall,
67
PC_in,
78
WB_En_in,
89
MEM_R_En_in,
@@ -22,10 +23,11 @@ module EXE_Stage_reg
2223
Immediate,
2324
ALU_result
2425
);
25-
26+
2627
// input and output ports
2728
input clk;
2829
input rst;
30+
input stall;
2931
input WB_En_in;
3032
input MEM_R_En_in;
3133
input MEM_W_En_in;
@@ -44,7 +46,7 @@ module EXE_Stage_reg
4446
output [31:0] PC;
4547
output [31:0] Immediate;
4648
output [31:0] ALU_result;
47-
49+
4850
// registers
4951
reg WB_En;
5052
reg MEM_R_En;
@@ -55,7 +57,7 @@ module EXE_Stage_reg
5557
reg [31:0] PC;
5658
reg [31:0] Immediate;
5759
reg [31:0] ALU_result;
58-
60+
5961
// build module
6062
always @(posedge clk)
6163
begin
@@ -73,16 +75,18 @@ module EXE_Stage_reg
7375
end
7476
else
7577
begin
76-
dest <= dest_in;
77-
PC <= PC_in;
78-
WB_En <= WB_En_in;
79-
MEM_R_En <= MEM_R_En_in;
80-
MEM_W_En <= MEM_W_En_in;
81-
Is_Imm <= Is_Imm_in;
82-
readdata <= readdata_in;
83-
Immediate <= Immediate_in;
84-
ALU_result <= ALU_result_in;
78+
if (~stall) begin
79+
dest <= dest_in;
80+
PC <= PC_in;
81+
WB_En <= WB_En_in;
82+
MEM_R_En <= MEM_R_En_in;
83+
MEM_W_En <= MEM_W_En_in;
84+
Is_Imm <= Is_Imm_in;
85+
readdata <= readdata_in;
86+
Immediate <= Immediate_in;
87+
ALU_result <= ALU_result_in;
88+
end
8589
end
8690
end
87-
91+
8892
endmodule

‎Sec_8/ForwardUnit.v

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21,12 +21,10 @@ module ForwardUnit
2121
shouldForward1,
2222
shouldForward2,
2323
);
24-
24+
2525
// define input and output ports
2626
input WB_En1;
2727
input WB_En2;
28-
//input Is_Imm1;
29-
//input Is_Imm2;
3028
input Is_Imm;
3129
input mem_W_En;
3230
input [1:0] BR_Type;
@@ -54,7 +52,7 @@ module ForwardUnit
5452
reg [31:0] srcOut2;
5553
reg [31:0] memOut;
5654

57-
// define branch types
55+
// define branch types
5856
parameter NO_BRANCH_Code = 2'b0;
5957
parameter BEZ_Code = 2'b01;
6058
parameter BNE_Code = 2'b10;
@@ -90,7 +88,7 @@ module ForwardUnit
9088
begin
9189
srcOut2 <= aluResult2;
9290
end
93-
91+
9492
if (shouldForwardMemFromExe)
9593
memOut <= aluResult1;
9694
else
@@ -100,4 +98,3 @@ module ForwardUnit
10098
memOut <= readdata2;
10199
end
102100
endmodule
103-

‎Sec_8/ID_Reg.v

Lines changed: 25 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ module ID_Stage_reg
3636
EXE_Cmd,
3737
PC
3838
);
39-
39+
4040
// input and output ports
4141
input clk;
4242
input rst;
@@ -72,7 +72,7 @@ module ID_Stage_reg
7272
output [31:0] data1;
7373
output [31:0] data2;
7474
output [31:0] PC;
75-
75+
7676
// registers
7777
reg [1:0] BR_Type;
7878
reg [3:0] EXE_Cmd;
@@ -89,13 +89,13 @@ module ID_Stage_reg
8989
reg MEM_R_En;
9090
reg MEM_W_En;
9191
reg [31:0] PC;
92-
92+
9393
// build module
94-
94+
9595
// pass instruction decode outputs
9696
always @(posedge clk)
9797
begin
98-
if(rst | branch_taken | stall)
98+
if(rst | branch_taken)
9999
begin
100100
dest <= 5'b0;
101101
readdata1 <= 32'b0;
@@ -116,23 +116,26 @@ module ID_Stage_reg
116116
end
117117
else
118118
begin
119-
dest <= dest_in;
120-
readdata1 <= readdata1_in;
121-
readdata2 <= readdata2_in;
122-
Is_Imm <= Is_Imm_in;
123-
Immediate <= Immediate_in;
124-
data1 <= data1_in;
125-
data2 <= data2_in;
126-
WB_En <= WB_En_in;
127-
MEM_R_En <= MEM_R_En_in;
128-
MEM_W_En <= MEM_W_En_in;
129-
BR_Type <= BR_Type_in;
130-
EXE_Cmd <= EXE_Cmd_in;
131-
PC <= PC_in;
132-
src1 <= src1_in;
133-
src2 <= src2_in;
134-
dest <= dest_in;
119+
if (~stall)
120+
begin
121+
dest <= dest_in;
122+
readdata1 <= readdata1_in;
123+
readdata2 <= readdata2_in;
124+
Is_Imm <= Is_Imm_in;
125+
Immediate <= Immediate_in;
126+
data1 <= data1_in;
127+
data2 <= data2_in;
128+
WB_En <= WB_En_in;
129+
MEM_R_En <= MEM_R_En_in;
130+
MEM_W_En <= MEM_W_En_in;
131+
BR_Type <= BR_Type_in;
132+
EXE_Cmd <= EXE_Cmd_in;
133+
PC <= PC_in;
134+
src1 <= src1_in;
135+
src2 <= src2_in;
136+
dest <= dest_in;
137+
end
135138
end
136139
end
137-
140+
138141
endmodule

‎Sec_8/MEM_Reg.v

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ module MEM_Stage_reg
33
(
44
clk,
55
rst,
6+
stall,
67
PC_in,
78
PC,
89
WB_En_in,
@@ -18,10 +19,11 @@ module MEM_Stage_reg
1819
ALU_result,
1920
Mem_Data
2021
);
21-
22+
2223
// input and output ports
2324
input clk;
2425
input rst;
26+
input stall;
2527
input WB_En_in;
2628
input MEM_R_En_in;
2729
input Is_Imm_in;
@@ -36,7 +38,7 @@ module MEM_Stage_reg
3638
output [31:0] PC;
3739
output [31:0] ALU_result;
3840
output [31:0] Mem_Data;
39-
41+
4042
// registers
4143
reg WB_En;
4244
reg MEM_R_En;
@@ -45,7 +47,7 @@ module MEM_Stage_reg
4547
reg [31:0] PC;
4648
reg [31:0] ALU_result;
4749
reg [31:0] Mem_Data;
48-
50+
4951
// build module
5052
always @(posedge clk)
5153
begin
@@ -61,14 +63,16 @@ module MEM_Stage_reg
6163
end
6264
else
6365
begin
64-
WB_En <= WB_En_in;
65-
MEM_R_En <= MEM_R_En_in;
66-
Is_Imm <= Is_Imm_in;
67-
dest <= dest_in;
68-
PC <= PC_in;
69-
ALU_result <= ALU_result_in;
70-
Mem_Data <= Mem_Data_in;
66+
if (~stall) begin
67+
WB_En <= WB_En_in;
68+
MEM_R_En <= MEM_R_En_in;
69+
Is_Imm <= Is_Imm_in;
70+
dest <= dest_in;
71+
PC <= PC_in;
72+
ALU_result <= ALU_result_in;
73+
Mem_Data <= Mem_Data_in;
74+
end
7175
end
7276
end
73-
77+
7478
endmodule

‎Sec_8/MIPS.v

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -6,22 +6,22 @@ module MIPS
66
rst,
77
Sel,
88
SRAMaddress, // SRAM Address bus 18 Bits
9-
SRAMWEn, // SRAM Write Enable
9+
SRAMWEn, // SRAM Write Enable
1010
SRAMOE, // SRAM Output Enable
1111
SRAMdata, // SRAM Data bus 16 Bits
1212
Instruction
1313
);
14-
14+
1515
// input and outputs
16-
input clk;
17-
input rst;
18-
input Sel;
19-
input SRAMWEn;
20-
input SRAMOE;
21-
input [17:0] SRAMaddress;
22-
output [5:0] Instruction;
16+
input clk;
17+
input rst;
18+
input Sel;
19+
output SRAMWEn;
20+
output SRAMOE;
21+
output [17:0] SRAMaddress;
22+
output [5:0] Instruction;
2323
inout [15:0] SRAMdata;
24-
24+
2525
// wires
2626
wire WB_En21;
2727
wire WB_En22;
@@ -86,12 +86,12 @@ module MIPS
8686
wire [31:0] ALU_Result42;
8787
wire [31:0] Mem_Data1;
8888
wire [31:0] Mem_Data2;
89-
89+
9090
// assemble modules
91-
91+
9292
// output
9393
assign Instruction = Instruction1[31:26];
94-
94+
9595
// instruction fetch
9696
IF_Stage IFS
9797
(
@@ -103,7 +103,7 @@ module MIPS
103103
.branch_taken(Branch_Taken),
104104
.PC(PC11)
105105
);
106-
106+
107107
// instruction fetch register
108108
IF_Stage_reg IFR
109109
(
@@ -116,7 +116,7 @@ module MIPS
116116
.Instruction(Instruction2),
117117
.PC(PC12)
118118
);
119-
119+
120120
// instruction decode
121121
ID_Stage IDS
122122
(
@@ -237,6 +237,7 @@ module MIPS
237237
(
238238
.clk(clk),
239239
.rst(rst),
240+
.stall(Stall),
240241
.PC_in(PC2),
241242
.PC(PC3),
242243
.WB_En_in(WB_En22),
@@ -278,6 +279,7 @@ module MIPS
278279
(
279280
.clk(clk),
280281
.rst(rst),
282+
.stall(Stall),
281283
.PC_in(PC3),
282284
.PC(PC4),
283285
.WB_En_in(WB_En32),
@@ -301,5 +303,5 @@ module MIPS
301303
.Mem_Data(Mem_Data2),
302304
.WB_Data(WB_Data)
303305
);
304-
306+
305307
endmodule

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