Skip to content

Commit 1da2da7

Browse files
author
Parham Farrokhi
committed
Use Pin Planner
1 parent f0e946e commit 1da2da7

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

41 files changed

+972905
-18
lines changed

Sec_6/MIPS.mpf

Lines changed: 18 additions & 18 deletions
Large diffs are not rendered by default.

Sec_6/MIPS.qpf

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
# -------------------------------------------------------------------------- #
2+
#
3+
# Copyright (C) 1991-2013 Altera Corporation
4+
# Your use of Altera Corporation's design tools, logic functions
5+
# and other software and tools, and its AMPP partner logic
6+
# functions, and any output files from any of the foregoing
7+
# (including device programming or simulation files), and any
8+
# associated documentation or information are expressly subject
9+
# to the terms and conditions of the Altera Program License
10+
# Subscription Agreement, Altera MegaCore Function License
11+
# Agreement, or other applicable license agreement, including,
12+
# without limitation, that your use is for the sole purpose of
13+
# programming logic devices manufactured by Altera and sold by
14+
# Altera or its authorized distributors. Please refer to the
15+
# applicable agreement for further details.
16+
#
17+
# -------------------------------------------------------------------------- #
18+
#
19+
# Quartus II 64-Bit
20+
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
21+
# Date created = 19:04:15 April 22, 2019
22+
#
23+
# -------------------------------------------------------------------------- #
24+
25+
QUARTUS_VERSION = "13.0"
26+
DATE = "19:04:15 April 22, 2019"
27+
28+
# Revisions
29+
30+
PROJECT_REVISION = "MIPS"

Sec_6/MIPS.qsf

Lines changed: 1696 additions & 0 deletions
Large diffs are not rendered by default.

Sec_6/MIPS.qws

613 Bytes
Binary file not shown.

Sec_6/MIPS_nativelink_simulation.rpt

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
Info: Start Nativelink Simulation process
2+
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
3+
4+
========= EDA Simulation Settings =====================
5+
6+
Sim Mode : RTL
7+
Family : cycloneii
8+
Quartus root : c:/altera/13.0sp1/quartus/bin64/
9+
Quartus sim root : c:/altera/13.0sp1/quartus/eda/sim_lib
10+
Simulation Tool : modelsim-altera
11+
Simulation Language : verilog
12+
Simulation Mode : GUI
13+
Sim Output File :
14+
Sim SDF file :
15+
Sim dir : simulation\modelsim
16+
17+
=======================================================
18+
19+
Info: Starting NativeLink simulation with ModelSim-Altera software
20+
Sourced NativeLink script c:/altera/13.0sp1/quartus/common/tcl/internal/nativelink/modelsim.tcl
21+
Info: Spawning ModelSim-Altera Simulation software

Sec_6/Sec_6.rar

10.3 KB
Binary file not shown.

Sec_6/simulation/modelsim/MIPS.sft

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
set tool_name "ModelSim-Altera (Verilog)"
2+
set corner_file_list {
3+
{{"Slow Model"} {MIPS.vo MIPS_v.sdo}}
4+
{{"Fast Model"} {MIPS_fast.vo MIPS_v_fast.sdo}}
5+
}

0 commit comments

Comments
 (0)