stall for ld dependency

Author: Parham Farrokhi

Sec_8/EXE_Reg.v

@@ -3,6 +3,7 @@ module EXE_Stage_reg
 	(
 			clk,
 			rst,
+			loadForwardStall,
 			superStall,
 			PC_in,
 			WB_En_in,
@@ -27,6 +28,7 @@ module EXE_Stage_reg
 	// input and output ports
 	input			clk;
 	input			rst;
+	input 		loadForwardStall;
 	input 		superStall;
 	input			WB_En_in;
 	input			MEM_R_En_in;
@@ -75,7 +77,7 @@ module EXE_Stage_reg
 		end
 		else
 		begin
-			if (~superStall) begin
+			if (~superStall & ~loadForwardStall) begin
 				dest <= dest_in;
 				PC <= PC_in;
 				WB_En <= WB_En_in;

Sec_8/ForwardUnit.v

@@ -5,6 +5,7 @@ module ForwardUnit
 		WB_En1,
 		WB_En2,
 		mem_W_En,
+		MEM_R_En,
 		Is_Imm,
 		src1,
 		src2,
@@ -25,6 +26,7 @@ module ForwardUnit
 	input			WB_En2;
 	input			Is_Imm;
 	input			mem_W_En;
+	input			mem_R_En;
 	input	[1:0]	BR_Type;
 	input	[4:0]	src1;
 	input	[4:0]	src2;
@@ -35,6 +37,7 @@ module ForwardUnit
 	input	[31:0]	aluResult2;
 	output 			shouldForward1;
 	output 			shouldForward2;
+	output  		loadForwardStall;
 	output	[31:0]	srcOut1;
 	output	[31:0]	srcOut2;
 	output	[31:0]	memOut;
@@ -64,6 +67,8 @@ module ForwardUnit
   assign shouldForwardMemWriteFromMem = !( src2 ^ dest2 ) & WB_En2 & mem_W_En & |dest2; //st
   assign shouldForward1 = shouldForward1FromExe | shouldForward1FromMem;
   assign shouldForward2 = shouldForward2FromExe | shouldForward2FromMem;
+
+	assign loadForwardStall = !( src2 ^ dest1 ) & WB_En1 & mem_R_En & |dest1;
 	// build module
 	always @(*)
 	begin

Sec_8/ID_Reg.v

@@ -4,6 +4,7 @@ module ID_Stage_reg
 		clk,
 		rst,
 		stall,
+		loadForwardStall,
 		superStall,
 		branch_taken,
 		src1_in,
@@ -42,6 +43,7 @@ module ID_Stage_reg
 	input			clk;
 	input			rst;
 	input			stall;
+	input 		loadForwardStall;
 	input 		superStall;
 	input			branch_taken;
 	input 			WB_En_in;
@@ -118,7 +120,7 @@ module ID_Stage_reg
 		end
 		else
 		begin
-			if (~stall & ~superStall)
+			if (~stall & ~superStall & ~loadForwardStall)
 			begin
 				dest <= dest_in;
 				readdata1 <= readdata1_in;

Sec_8/IF.v

@@ -4,6 +4,7 @@ module IF_Stage
 		clk,
 		rst,
 		stall,
+		loadForwardStall,
 		superStall,
 		Instruction,
 		branch_taken,
@@ -15,6 +16,7 @@ module IF_Stage
 	input			clk;
 	input			rst;
 	input			stall;
+	input 		loadForwardStall;
 	input 		superStall;
 	input 			branch_taken;
 	input	[31:0]	branch_address;
@@ -37,7 +39,7 @@ module IF_Stage
 			if(branch_taken)
 					PC <= branch_address;
 			else
-				if( ~stall & ~superStall )
+				if( ~stall & ~superStall & ~loadForwardStall )
 					PC <= PC + 4;
 		end
 	end

Sec_8/IF_Reg.v

@@ -4,6 +4,7 @@ module IF_Stage_reg
 		clk,
 		rst,
 		stall,
+		loadForwardStall,
 		superStall,
 		branch_taken,
 		Instruction_in,
@@ -16,6 +17,7 @@ module IF_Stage_reg
 	input			clk;
 	input			rst;
 	input			stall;
+	input 		loadForwardStall;
 	input 		superStall;
 	input			branch_taken;
 	input	[31:0]	Instruction_in;
@@ -40,7 +42,7 @@ module IF_Stage_reg
 		end
 		else
 		begin
-			if( ~stall & ~superStall )
+			if( ~stall & ~superStall & ~loadForwardStall)
 			begin
 				Instruction <= Instruction_in;
 				PC <= PC_in;

Sec_8/MIPS.v

@@ -39,6 +39,7 @@ module MIPS
 	wire 			Branch_Taken;
 	wire			SRAM_NOT_READY;
 	wire			Stall;
+	wire 			loadForwardStall;
 	wire 			superStall;
 	wire	[1:0]	BR_Type1;
 	wire	[1:0]	BR_Type2;
@@ -91,6 +92,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.loadForwardStall(loadForwardStall),
 			.superStall(superStall),
 			.branch_address(Branch_Address),
 			.Instruction(Instruction1),
@@ -104,6 +106,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.loadForwardStall(loadForwardStall),
 			.superStall(superStall),
 			.branch_taken(Branch_Taken),
 			.Instruction_in(Instruction1),
@@ -158,6 +161,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.loadForwardStall(loadForwardStall),
 			.superStall(superStall),
 			.branch_taken(Branch_Taken),
 			.readdata1_in(readdata11),
@@ -192,25 +196,27 @@ module MIPS
 			.PC(PC2)
 		);
 	ForwardUnit FU
-	    (
-            .BR_Type(BR_Type2), // Pass BR_Type through levels
-            .WB_En1(WB_En32),
-            .WB_En2(WB_En42),
+    (
+      .BR_Type(BR_Type2), // Pass BR_Type through levels
+      .WB_En1(WB_En32),
+      .WB_En2(WB_En42),
 			.mem_W_En(MEM_W_En22),
-            .Is_Imm(Is_Imm2),
-            .src1(src12),
-            .src2(src22),
+			.MEM_R_En(MEM_R_En22),
+      .Is_Imm(Is_Imm2),
+      .src1(src12),
+      .src2(src22),
 			.readdata2(readdata22),
-            .dest1(dest3),
-            .dest2(dest4),
-            .aluResult1(WB_Data0),
-            .aluResult2(WB_Data),
-            .srcOut1(forwardVal11),
-            .srcOut2(forwardVal12),
+      .dest1(dest3),
+      .dest2(dest4),
+      .aluResult1(WB_Data0),
+      .aluResult2(WB_Data),
+      .srcOut1(forwardVal11),
+      .srcOut2(forwardVal12),
 			.memOut(memForwardVal),
-            .shouldForward1(shouldForward11),
-            .shouldForward2(shouldForward12)
-        );
+      .shouldForward1(shouldForward11),
+      .shouldForward2(shouldForward12),
+			.loadForwardStall(loadForwardStall)
+    );
 	// execution
 	EXE_Stage EXES
 		(
@@ -234,6 +240,7 @@ module MIPS
 		(
 			.clk(clk),
 			.rst(rst),
+			.loadForwardStall(loadForwardStall),
 			.superStall(superStall),
 			.PC_in(PC2),
 			.PC(PC3),

Sec_8/MIPSHQ.v

@@ -309,7 +309,7 @@ MIPS UUT
 		.Sel(SW[1]),
 		.SRAMdata( SRAM_DQ ),							//	SRAM Data bus 16 Bits
 		.SRAMaddress( SRAM_ADDR ),				//	SRAM Address bus 18 Bits
-		.SRAMWEn( SRAM_WE_N ),						//	SRAM Write Enable
+		.SRAMWEn( SRAM_WE_N ) 						//	SRAM Write Enable
 	);
 
 	assign SRAM_UB_N = 1'b0;			//	SRAM High-byte Data Mask