Divide stall for SRAM and HazardUnit, use superStall

Author: mr-bat

Sec_8/EXE_Reg.v

@@ -4,6 +4,7 @@ module EXE_Stage_reg
 			clk,
 			rst,
 			stall,
+			superStall,
 			PC_in,
 			WB_En_in,
 			MEM_R_En_in,
@@ -28,6 +29,7 @@ module EXE_Stage_reg
 	input			clk;
 	input			rst;
 	input 		stall;
+	input 		superStall;
 	input			WB_En_in;
 	input			MEM_R_En_in;
 	input			MEM_W_En_in;
@@ -75,7 +77,7 @@ module EXE_Stage_reg
 		end
 		else
 		begin
-			if (~stall) begin
+			if (~superStall) begin
 				dest <= dest_in;
 				PC <= PC_in;
 				WB_En <= WB_En_in;
@@ -84,7 +86,7 @@ module EXE_Stage_reg
 				Is_Imm <= Is_Imm_in;
 				readdata <= readdata_in;
 				Immediate <= Immediate_in;
-				ALU_result <= ALU_result_in;				
+				ALU_result <= ALU_result_in;
 			end
 		end
 	end

Sec_8/Hazard.v

@@ -11,7 +11,8 @@ module Hazard
 		src2,
 		dest1,
 		dest2,
-		Stall
+		Stall,
+		superStall
 	);
 
 	// define input and output ports
@@ -26,12 +27,13 @@ module Hazard
 	input	[4:0]	dest1;
 	input	[4:0]	dest2;
 	output			Stall;
+	output 			superStall;
 
 	// wires and registers
-	wire        shouldForward1FromExe;
-	wire        shouldForward2FromExe;
-	wire        shouldForward1FromMem;
-	wire        shouldForward2FromMem;
+	wire    shouldForward1FromExe;
+	wire    shouldForward2FromExe;
+	wire    shouldForward1FromMem;
+	wire    shouldForward2FromMem;
 	wire		shouldForwardMemFromExe;
 	wire		shouldForwardMemFromMem;
 
@@ -51,10 +53,8 @@ module Hazard
 	assign shouldForward2 = shouldForward2FromExe | shouldForward2FromMem;
 
 	// build module
-	assign Stall = (
-						shouldForward1 |
-						shouldForward2 &
-						Sel
-				  ) | SRAM_NOT_READY ;
+	assign Stall = ( shouldForward1 | shouldForward2) & Sel;
+	assign superStall = SRAM_NOT_READY;
+
 
 endmodule

Sec_8/ID_Reg.v

@@ -4,6 +4,7 @@ module ID_Stage_reg
 		clk,
 		rst,
 		stall,
+		superStall,
 		branch_taken,
 		src1_in,
 		src2_in,
@@ -41,6 +42,7 @@ module ID_Stage_reg
 	input			clk;
 	input			rst;
 	input			stall;
+	input 		superStall;
 	input			branch_taken;
 	input 			WB_En_in;
 	input 			MEM_R_En_in;
@@ -116,7 +118,7 @@ module ID_Stage_reg
 		end
 		else
 		begin
-			if (~stall)
+			if (~stall | ~superStall)
 			begin
 				dest <= dest_in;
 				readdata1 <= readdata1_in;

Sec_8/IF_Reg.v

@@ -4,30 +4,32 @@ module IF_Stage_reg
 		clk,
 		rst,
 		stall,
+		superStall,
 		branch_taken,
 		Instruction_in,
 		PC_in,
 		Instruction,
 		PC
 	);
-	
+
 	// input and outputs
 	input			clk;
 	input			rst;
 	input			stall;
+	input 		superStall;
 	input			branch_taken;
 	input	[31:0]	Instruction_in;
 	input	[31:0]	PC_in;
 	output	[31:0]	Instruction;
 	output	[31:0]	PC;
 
-	
+
 	// registers
 	reg		[31:0]	Instruction;
 	reg		[31:0]	PC;
-	
+
 	// build module
-	
+
 	// transition	between
 	always @(posedge clk)
 	begin
@@ -38,12 +40,12 @@ module IF_Stage_reg
 		end
 		else
 		begin
-			if( ~stall )
+			if( ~stall | ~superStall )
 			begin
 				Instruction <= Instruction_in;
 				PC <= PC_in;
 			end
 		end
 	end
-	
+
 endmodule

Sec_8/MEM_Reg.v

@@ -4,6 +4,7 @@ module MEM_Stage_reg
 			clk,
 			rst,
 			stall,
+			superStall,
 			PC_in,
 			PC,
 			WB_En_in,
@@ -24,6 +25,7 @@ module MEM_Stage_reg
 	input			clk;
 	input			rst;
 	input 		stall;
+	input 		superStall;
 	input			WB_En_in;
 	input			MEM_R_En_in;
 	input           Is_Imm_in;
@@ -63,7 +65,7 @@ module MEM_Stage_reg
 		end
 		else
 		begin
-			if (~stall) begin
+			if (~superStall) begin
 				WB_En <= WB_En_in;
 				MEM_R_En <= MEM_R_En_in;
 				Is_Imm <= Is_Imm_in;

Sec_8/MIPS.v

@@ -44,6 +44,7 @@ module MIPS
 	wire 			Branch_Taken;
 	wire			SRAM_NOT_READY;
 	wire			Stall;
+	wire 			superStall;
 	wire	[1:0]	BR_Type1;
 	wire	[1:0]	BR_Type2;
 	wire	[4:0]	src11;
@@ -110,6 +111,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.superStall(superStall),
 			.branch_taken(Branch_Taken),
 			.Instruction_in(Instruction1),
 			.PC_in(PC11),
@@ -154,14 +156,16 @@ module MIPS
 			.src2(src21),
 			.dest1(dest2),
 			.dest2(dest3),
-			.Stall(Stall)
+			.Stall(Stall),
+			.superStall(superStall)
 		);
 	// instruction decode register
 	ID_Stage_reg IDR
 		(
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.superStall(superStall),
 			.branch_taken(Branch_Taken),
 			.readdata1_in(readdata11),
 			.readdata2_in(readdata21),
@@ -238,6 +242,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.superStall(superStall),
 			.PC_in(PC2),
 			.PC(PC3),
 			.WB_En_in(WB_En22),
@@ -280,6 +285,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.superStall(superStall),
 			.PC_in(PC3),
 			.PC(PC4),
 			.WB_En_in(WB_En32),