Remove Stall signal & SRAMOE, Refactor state machine sram controller

Author: Parham Farrokhi

Sec_8/EXE_Reg.v

@@ -3,7 +3,6 @@ module EXE_Stage_reg
 	(
 			clk,
 			rst,
-			stall,
 			superStall,
 			PC_in,
 			WB_En_in,
@@ -28,7 +27,6 @@ module EXE_Stage_reg
 	// input and output ports
 	input			clk;
 	input			rst;
-	input 		stall;
 	input 		superStall;
 	input			WB_En_in;
 	input			MEM_R_En_in;

Sec_8/MEM.v

@@ -10,7 +10,6 @@ module MEM_Stage
 		SRAM_NOT_READY,
 		SRAMaddress,
 		SRAMWEn,
-		SRAMOE,
 		readdata,
 		wbData,
 		SRAMdata,
@@ -22,7 +21,6 @@ module MEM_Stage
 	input			read;
 	input			write;
 	output 		SRAMWEn;
-	output 		SRAMOE;
 	input	[31:0]	aluResult;
 	input	[31:0]	writedata;
 	output [17:0]	SRAMaddress;
@@ -54,16 +52,15 @@ module MEM_Stage
 			.rst(rst),
 			.SRAMaddress(SRAMaddress),
 			.SRAMWEn(SRAMWEn),
-			.SRAMOE(SRAMOE),
 			.SRAMdata(SRAMdata),
 			.SRAM_NOT_READY(SRAM_NOT_READY),
 			.writeData(writedata),
 			.address(realaddress),
-			.readData(readData)
+			.readData(readdata)
 		);
 
 	// assign SRAM_NOT_READY = 1'b0;
-	// assign readdata = (read) ? registers[realaddress[7:0]] : 32'b0;
+	//assign readdata = (read) ? registers[realaddress[7:0]] : 32'b0;
 	assign wbData = (read) ? readdata : aluResult;
 
 	// write part

Sec_8/MEM_Reg.v

@@ -3,7 +3,6 @@ module MEM_Stage_reg
 	(
 			clk,
 			rst,
-			stall,
 			superStall,
 			PC_in,
 			PC,
@@ -24,7 +23,6 @@ module MEM_Stage_reg
 	// input and output ports
 	input			clk;
 	input			rst;
-	input 		stall;
 	input 		superStall;
 	input			WB_En_in;
 	input			MEM_R_En_in;

Sec_8/MIPS.mpf

@@ -6,20 +6,16 @@ module MIPS
 		rst,
 		Sel,
 		SRAMaddress, 	//	SRAM Address bus 18 Bits
-		SRAMWEn, 		//	SRAM Write Enable
-		SRAMOE, 		// 	SRAM Output Enable
+		SRAMWEn, 			//	SRAM Write Enable
 		SRAMdata, 		//	SRAM Data bus 16 Bits
-		Instruction
 	);
 
 	// input and outputs
 	input					clk;
 	input					rst;
 	input					Sel;
 	output  			SRAMWEn;
-	output 				SRAMOE;
 	output [17:0]	SRAMaddress;
-	output [5:0]	Instruction;
 	inout	[15:0]	SRAMdata;
 
 	// wires
@@ -38,9 +34,8 @@ module MIPS
 	wire			Is_Imm2;
 	wire			Is_Imm3;
 	wire			Is_Imm4;
-	wire            shouldForward11;
-	wire            shouldForward12;
-	wire			shouldForward1mem;
+	wire      shouldForward11;
+	wire      shouldForward12;
 	wire 			Branch_Taken;
 	wire			SRAM_NOT_READY;
 	wire			Stall;
@@ -90,9 +85,6 @@ module MIPS
 
 	// assemble modules
 
-	// output
-	assign Instruction = Instruction1[31:26];
-
 	// instruction fetch
 	IF_Stage IFS
 		(
@@ -199,7 +191,6 @@ module MIPS
 			.EXE_Cmd(EXE_Cmd2),
 			.PC(PC2)
 		);
-	// execution
 	ForwardUnit FU
 	    (
             .BR_Type(BR_Type2), // Pass BR_Type through levels
@@ -220,6 +211,7 @@ module MIPS
             .shouldForward1(shouldForward11),
             .shouldForward2(shouldForward12)
         );
+	// execution
 	EXE_Stage EXES
 		(
 			.BR_Type(BR_Type2),
@@ -242,7 +234,6 @@ module MIPS
 		(
 			.clk(clk),
 			.rst(rst),
-			.stall(Stall),
 			.superStall(superStall),
 			.PC_in(PC2),
 			.PC(PC3),
@@ -276,7 +267,6 @@ module MIPS
 			.wbData(WB_Data0),
 			.SRAMaddress( SRAMaddress ),
 			.SRAMWEn( SRAMWEn ),
-			.SRAMOE( SRAMOE ),
 			.SRAM_NOT_READY( SRAM_NOT_READY ),
 			.SRAMdata( SRAMdata )
 		);
@@ -285,7 +275,6 @@ module MIPS
 		(
 			.clk(clk),
 			.rst(rst),
-			.stall(Stall),
 			.superStall(superStall),
 			.PC_in(PC3),
 			.PC(PC4),

Sec_8/MIPS.qsf

@@ -5,8 +5,8 @@
 // Permission:
 //
 //   Terasic grants permission to use and modify this code for use
-//   in synthesis for all Terasic Development Boards and Altera Development 
-//   Kits made by Terasic.  Other use of this code, including the selling 
+//   in synthesis for all Terasic Development Boards and Altera Development
+//   Kits made by Terasic.  Other use of this code, including the selling
 //   ,duplication, or modification of any portion is strictly prohibited.
 //
 // Disclaimer:
@@ -15,11 +15,11 @@
 //   which illustrates how these types of functions can be implemented.
 //   It is the user's responsibility to verify their design for
 //   consistency and functionality through the use of formal
-//   verification methods.  Terasic provides no warranty regarding the use 
+//   verification methods.  Terasic provides no warranty regarding the use
 //   or functionality of this code.
 //
 // ============================================================================
-//           
+//
 //  Terasic Technologies Inc
 //  9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
 //
@@ -39,15 +39,15 @@
 //   Ver  :| Author            :| Mod. Date :| Changes Made:
 //   V1.0 :| Johnny Chen       :| 05/08/19  :|      Initial Revision
 //   V1.1 :| Johnny Chen       :| 05/11/16  :|      Added FLASH Address FL_ADDR[21:20]
-//   V1.2 :| Johnny Chen       :| 05/11/16  :|		Fixed ISP1362 INT/DREQ Pin Direction.   
+//   V1.2 :| Johnny Chen       :| 05/11/16  :|		Fixed ISP1362 INT/DREQ Pin Direction.
 //   V1.3 :| Johnny Chen       :| 06/11/16  :|		Added the Dedicated TV Decoder Line-Locked-Clock Input
 //													            for DE2 v2.X PCB.
 //   V1.5 :| Eko    Yan        :| 12/01/30  :|      Update to version 11.1 sp1.
 // ============================================================================
 
 module MIPSHQ
 	(
-		////////////////////	Clock Input	 	////////////////////	 
+		////////////////////	Clock Input	 	////////////////////
 		CLOCK_27,						//	27 MHz
 		CLOCK_50,						//	50 MHz
 		EXT_CLOCK,						//	External Clock
@@ -76,7 +76,7 @@ module MIPSHQ
 		/////////////////////	SDRAM Interface		////////////////
 		DRAM_DQ,						//	SDRAM Data bus 16 Bits
 		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
-		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask
 		DRAM_UDQM,						//	SDRAM High-byte Data Mask
 		DRAM_WE_N,						//	SDRAM Write Enable
 		DRAM_CAS_N,						//	SDRAM Column Address Strobe
@@ -96,8 +96,8 @@ module MIPSHQ
 		////////////////////	SRAM Interface		////////////////
 		SRAM_DQ,						//	SRAM Data bus 16 Bits
 		SRAM_ADDR,						//	SRAM Address bus 18 Bits
-		SRAM_UB_N,						//	SRAM High-byte Data Mask 
-		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
+		SRAM_UB_N,						//	SRAM High-byte Data Mask
+		SRAM_LB_N,						//	SRAM Low-byte Data Mask
 		SRAM_WE_N,						//	SRAM Write Enable
 		SRAM_CE_N,						//	SRAM Chip Enable
 		SRAM_OE_N,						//	SRAM Output Enable
@@ -125,7 +125,7 @@ module MIPSHQ
 		LCD_DATA,						//	LCD Data bus 8 bits
 		////////////////////	SD_Card Interface	////////////////
 		//SD_DAT,							//	SD Card Data
-		//SD_WP_N,						   //	SD Write protect 
+		//SD_WP_N,						   //	SD Write protect
 		//SD_CMD,							//	SD Card Command Signal
 		//SD_CLK,							//	SD Card Clock
 		////////////////////	USB JTAG link	////////////////////
@@ -204,7 +204,7 @@ output  [17:0]	LEDR;					//	LED Red[17:0]
 ///////////////////////		SDRAM Interface	////////////////////////
 inout	  [15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
 output  [11:0]	DRAM_ADDR;				//	SDRAM Address bus 12 Bits
-output			DRAM_LDQM;				//	SDRAM Low-byte Data Mask 
+output			DRAM_LDQM;				//	SDRAM Low-byte Data Mask
 output			DRAM_UDQM;				//	SDRAM High-byte Data Mask
 output			DRAM_WE_N;				//	SDRAM Write Enable
 output			DRAM_CAS_N;				//	SDRAM Column Address Strobe
@@ -224,8 +224,8 @@ output			FL_CE_N;				//	FLASH Chip Enable
 ////////////////////////	SRAM Interface	////////////////////////
 inout	 [15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
 output [17:0]	SRAM_ADDR;				//	SRAM Address bus 18 Bits
-output			SRAM_UB_N;				//	SRAM High-byte Data Mask 
-output			SRAM_LB_N;				//	SRAM Low-byte Data Mask 
+output			SRAM_UB_N;				//	SRAM High-byte Data Mask
+output			SRAM_LB_N;				//	SRAM Low-byte Data Mask
 output			SRAM_WE_N;				//	SRAM Write Enable
 output			SRAM_CE_N;				//	SRAM Chip Enable
 output			SRAM_OE_N;				//	SRAM Output Enable
@@ -307,16 +307,14 @@ MIPS UUT
 		.clk(CLOCK_50),
 		.rst(SW[0]),
 		.Sel(SW[1]),
-		.SRAMdata( SRAM_DQ ),						//	SRAM Data bus 16 Bits
-		.SRAMaddress( SRAM_ADDR ),					//	SRAM Address bus 18 Bits
-		.SRAMWEn( SRAM_WE_N ),						//	SRAM Write Enable	
-		.SRAMOE( SRAM_OE_N ),						// 	SRAM Output Enable
-		.Instruction(LEDR[5:0])
+		.SRAMdata( SRAM_DQ ),							//	SRAM Data bus 16 Bits
+		.SRAMaddress( SRAM_ADDR ),				//	SRAM Address bus 18 Bits
+		.SRAMWEn( SRAM_WE_N ),						//	SRAM Write Enable
 	);
 
-	assign SRAM_UB_N = 1'b0;			//	SRAM High-byte Data Mask 
-	assign SRAM_LB_N = 1'b0;			//	SRAM Low-byte Data Mask 
+	assign SRAM_UB_N = 1'b0;			//	SRAM High-byte Data Mask
+	assign SRAM_LB_N = 1'b0;			//	SRAM Low-byte Data Mask
 	assign SRAM_CE_N = 1'b0;			//	SRAM Chip Enable
-		
-endmodule
+	assign SRAM_OE_N = 1'b0;			// 	SRAM Output Enable
 
+endmodule