Fix wrong input/output

Author: mr-bat

Sec_8/Hazard.v

@@ -13,7 +13,7 @@ module Hazard
 		dest2,
 		Stall
 	);
-	
+
 	// define input and output ports
 	input			Sel;
 	input			WB_En1;
@@ -27,19 +27,34 @@ module Hazard
 	input	[4:0]	dest2;
 	output			Stall;
 
-	// define branch types	
+	// wires and registers
+	wire        shouldForward1FromExe;
+	wire        shouldForward2FromExe;
+	wire        shouldForward1FromMem;
+	wire        shouldForward2FromMem;
+	wire		shouldForwardMemFromExe;
+	wire		shouldForwardMemFromMem;
+
+	// define branch types
 	parameter NO_BRANCH_Code = 2'b0;
 	parameter BEZ_Code = 2'b01;
 	parameter BNE_Code = 2'b10;
 	parameter JMP_Code = 2'b11;
-	
+
+	assign shouldForward1FromExe = !( src1 ^ dest1 ) & WB_En1 & |dest1;
+	assign shouldForward2FromExe = !( src2 ^ dest1 ) & WB_En1 & (~Is_Imm | !(BR_Type ^ BNE_Code)) & |dest1;
+	// assign shouldForwardMemFromExe = !( src2 ^ dest1 ) & WB_En1 & mem_W_En  & |dest1;
+	assign shouldForward1FromMem = ((!( src1 ^ dest2 )) & WB_En2) & (|dest2);
+	assign shouldForward2FromMem = ((!( src2 ^ dest2 )) & WB_En2 & (~Is_Imm | !(BR_Type ^ BNE_Code))) & |dest2;
+	// assign shouldForwardMemFromMem = !( src2 ^ dest2 ) & WB_En2 & mem_W_En & |dest2;
+	assign shouldForward1 = shouldForward1FromExe | shouldForward1FromMem;
+	assign shouldForward2 = shouldForward2FromExe | shouldForward2FromMem;
+
 	// build module
 	assign Stall = (
-					( ( |src1 & !( src1 ^ dest1 ) & WB_En1 ) |
-					( |src2 & !( src2 ^ dest1 ) & WB_En1 & (~Is_Imm | !(BR_Type ^ BNE_Code) ) ) |
-					( |src1 & !( src1 ^ dest2 ) & WB_En2 )  |
-					( |src2 & !( src2 ^ dest2 ) & WB_En2 & (~Is_Imm | !(BR_Type ^ BNE_Code) ) ) ) &
-					Sel
-				   ) | SRAM_NOT_READY ;
-	
+						shouldForward1 |
+						shouldForward2 &
+						Sel
+				  ) | SRAM_NOT_READY ;
+
 endmodule

Sec_8/MEM.v

@@ -61,15 +61,18 @@ module MEM_Stage
 			.address(realaddress),
 			.readData(readData)
 		);
-//	assign readdata = (read) ? registers[realaddress[7:0]] : 32'b0;
+
+	// assign SRAM_NOT_READY = 1'b0;
+	// assign readdata = (read) ? registers[realaddress[7:0]] : 32'b0;
 	assign wbData = (read) ? readdata : aluResult;
+
 	// write part
-	/* always @(posedge clk)
-	begin
-		if(write)
-		begin
-			registers[realaddress] <= writedata;
-		end
-	end */
+	// always @(posedge clk)
+	// begin
+	// 	if(write)
+	// 	begin
+	// 		registers[realaddress] <= writedata;
+	// 	end
+	// end
 
 endmodule

Sec_8/MIPS.v

@@ -6,22 +6,22 @@ module MIPS
 		rst,
 		Sel,
 		SRAMaddress, 	//	SRAM Address bus 18 Bits
-		SRAMWEn, 		//	SRAM Write Enable	
+		SRAMWEn, 		//	SRAM Write Enable
 		SRAMOE, 		// 	SRAM Output Enable
 		SRAMdata, 		//	SRAM Data bus 16 Bits
 		Instruction
 	);
-	
+
 	// input and outputs
 	input			clk;
 	input			rst;
 	input			Sel;
-	input 			SRAMWEn;
-	input			SRAMOE;
-	input	[17:0]	SRAMaddress;
+	output  	SRAMWEn;
+	output 		SRAMOE;
+	output [17:0]	SRAMaddress;
 	output	[5:0]	Instruction;
 	inout	[15:0]	SRAMdata;
-	
+
 	// wires
 	wire 			WB_En21;
 	wire			WB_En22;
@@ -86,12 +86,12 @@ module MIPS
 	wire	[31:0]	ALU_Result42;
 	wire	[31:0]	Mem_Data1;
 	wire	[31:0]	Mem_Data2;
-	
+
 	// assemble modules
-	
+
 	// output
 	assign Instruction = Instruction1[31:26];
-	
+
 	// instruction fetch
 	IF_Stage IFS
 		(
@@ -103,7 +103,7 @@ module MIPS
 			.branch_taken(Branch_Taken),
 			.PC(PC11)
 		);
-		
+
 	// instruction fetch register
 	IF_Stage_reg IFR
 		(
@@ -116,7 +116,7 @@ module MIPS
 			.Instruction(Instruction2),
 			.PC(PC12)
 		);
-		
+
 	// instruction decode
 	ID_Stage IDS
 		(
@@ -301,5 +301,5 @@ module MIPS
 			.Mem_Data(Mem_Data2),
 			.WB_Data(WB_Data)
 		);
-	
+
 endmodule

Sec_8/Test.v

@@ -6,20 +6,28 @@ module test;
 	reg				rst;
 	reg				Sel;
 	wire	[5:0]	Instruction;
-	
+	wire 	[17:0] SRAMaddress;
+	wire SRAMWEn;
+	wire SRAMOE;
+	wire [15:0] SRAMdata;
+
 	// module under test
 	MIPS UUT
 	(
 		clk,
 		rst,
 		Sel,
+		SRAMaddress, 	//	SRAM Address bus 18 Bits
+		SRAMWEn, 		//	SRAM Write Enable
+		SRAMOE, 		// 	SRAM Output Enable
+		SRAMdata, 		//	SRAM Data bus 16 Bits
 		Instruction
 	);
-	
+
 	// write a test
-	
+
 	initial repeat (900) #(10) clk = ~clk;
-	
+
 	initial
 	begin
 				clk = 0; 	rst = 0;	Sel = 0;
@@ -29,5 +37,5 @@ module test;
 		#( 35 ) rst = 1;
 		#( 40 ) rst = 0;
 	end
-	
+
 endmodule