Merge branch 'master' of github.com:mr-bat/Computer_Architecture_Lab

Author: mr-bat

Sec_8/EXE_Reg.v

@@ -3,6 +3,7 @@ module EXE_Stage_reg
 	(
 			clk,
 			rst,
+			stall,
 			PC_in,
 			WB_En_in,
 			MEM_R_En_in,
@@ -22,10 +23,11 @@ module EXE_Stage_reg
 			Immediate,
 			ALU_result
 	);
-	
+
 	// input and output ports
 	input			clk;
 	input			rst;
+	input 		stall;
 	input			WB_En_in;
 	input			MEM_R_En_in;
 	input			MEM_W_En_in;
@@ -44,7 +46,7 @@ module EXE_Stage_reg
 	output	[31:0]	PC;
 	output	[31:0]	Immediate;
 	output	[31:0]	ALU_result;
-	
+
 	// registers
 	reg				WB_En;
 	reg				MEM_R_En;
@@ -55,7 +57,7 @@ module EXE_Stage_reg
 	reg		[31:0]	PC;
 	reg		[31:0]	Immediate;
 	reg		[31:0]	ALU_result;
-	
+
 	// build module
 	always @(posedge clk)
 	begin
@@ -73,16 +75,18 @@ module EXE_Stage_reg
 		end
 		else
 		begin
-			dest <= dest_in;
-			PC <= PC_in;
-			WB_En <= WB_En_in;
-			MEM_R_En <= MEM_R_En_in;
-			MEM_W_En <= MEM_W_En_in;
-			Is_Imm <= Is_Imm_in;
-			readdata <= readdata_in;
-			Immediate <= Immediate_in;
-			ALU_result <= ALU_result_in;
+			if (~stall) begin
+				dest <= dest_in;
+				PC <= PC_in;
+				WB_En <= WB_En_in;
+				MEM_R_En <= MEM_R_En_in;
+				MEM_W_En <= MEM_W_En_in;
+				Is_Imm <= Is_Imm_in;
+				readdata <= readdata_in;
+				Immediate <= Immediate_in;
+				ALU_result <= ALU_result_in;				
+			end
 		end
 	end
-	
+
 endmodule

Sec_8/ForwardUnit.v

@@ -21,12 +21,10 @@ module ForwardUnit
 		shouldForward1,
 		shouldForward2,
 	);
-	
+
 	// define input and output ports
 	input			WB_En1;
 	input			WB_En2;
-	//input			Is_Imm1;
-	//input			Is_Imm2;
 	input			Is_Imm;
 	input			mem_W_En;
 	input	[1:0]	BR_Type;
@@ -54,7 +52,7 @@ module ForwardUnit
 	reg	[31:0]	srcOut2;
 	reg	[31:0]	memOut;
 
-	// define branch types	
+	// define branch types
 	parameter NO_BRANCH_Code = 2'b0;
 	parameter BEZ_Code = 2'b01;
 	parameter BNE_Code = 2'b10;
@@ -90,7 +88,7 @@ module ForwardUnit
             begin
                 srcOut2 <= aluResult2;
             end
-		
+
 		if (shouldForwardMemFromExe)
 			memOut <= aluResult1;
 		else
@@ -100,4 +98,3 @@ module ForwardUnit
 				memOut <= readdata2;
 	end
 endmodule
-

Sec_8/ID_Reg.v

@@ -36,7 +36,7 @@ module ID_Stage_reg
 		EXE_Cmd,
 		PC
 	);
-	
+
 	// input and output ports
 	input			clk;
 	input			rst;
@@ -72,7 +72,7 @@ module ID_Stage_reg
 	output 	[31:0]	data1;
 	output 	[31:0]	data2;
 	output	[31:0]	PC;
-	
+
 	// registers
 	reg 	[1:0]	BR_Type;
 	reg 	[3:0]	EXE_Cmd;
@@ -89,13 +89,13 @@ module ID_Stage_reg
 	reg 			MEM_R_En;
 	reg 			MEM_W_En;
 	reg		[31:0]	PC;
-	
+
 	// build module
-	
+
 	// pass instruction decode outputs
 	always @(posedge clk)
 	begin
-		if(rst | branch_taken | stall)
+		if(rst | branch_taken)
 		begin
 			dest <= 5'b0;
 			readdata1 <= 32'b0;
@@ -116,23 +116,26 @@ module ID_Stage_reg
 		end
 		else
 		begin
-			dest <= dest_in;
-			readdata1 <= readdata1_in;
-			readdata2 <= readdata2_in;
-			Is_Imm <= Is_Imm_in;
-			Immediate <= Immediate_in;
-			data1 <= data1_in;
-			data2 <= data2_in;
-			WB_En <= WB_En_in;
-			MEM_R_En <= MEM_R_En_in;
-			MEM_W_En <= MEM_W_En_in;
-			BR_Type <= BR_Type_in;
-			EXE_Cmd <= EXE_Cmd_in;
-			PC <= PC_in;
-			src1 <= src1_in;
-			src2 <= src2_in;
-			dest <= dest_in;
+			if (~stall)
+			begin
+				dest <= dest_in;
+				readdata1 <= readdata1_in;
+				readdata2 <= readdata2_in;
+				Is_Imm <= Is_Imm_in;
+				Immediate <= Immediate_in;
+				data1 <= data1_in;
+				data2 <= data2_in;
+				WB_En <= WB_En_in;
+				MEM_R_En <= MEM_R_En_in;
+				MEM_W_En <= MEM_W_En_in;
+				BR_Type <= BR_Type_in;
+				EXE_Cmd <= EXE_Cmd_in;
+				PC <= PC_in;
+				src1 <= src1_in;
+				src2 <= src2_in;
+				dest <= dest_in;
+			end
 		end
 	end
-	
+
 endmodule

Sec_8/MEM_Reg.v

@@ -3,6 +3,7 @@ module MEM_Stage_reg
 	(
 			clk,
 			rst,
+			stall,
 			PC_in,
 			PC,
 			WB_En_in,
@@ -18,10 +19,11 @@ module MEM_Stage_reg
 			ALU_result,
 			Mem_Data
 	);
-	
+
 	// input and output ports
 	input			clk;
 	input			rst;
+	input 		stall;
 	input			WB_En_in;
 	input			MEM_R_En_in;
 	input           Is_Imm_in;
@@ -36,7 +38,7 @@ module MEM_Stage_reg
 	output	[31:0]	PC;
 	output	[31:0]	ALU_result;
 	output	[31:0]	Mem_Data;
-	
+
 	// registers
 	reg				WB_En;
 	reg				MEM_R_En;
@@ -45,7 +47,7 @@ module MEM_Stage_reg
 	reg		[31:0]	PC;
 	reg		[31:0]	ALU_result;
 	reg		[31:0]	Mem_Data;
-	
+
 	// build module
 	always @(posedge clk)
 	begin
@@ -61,14 +63,16 @@ module MEM_Stage_reg
 		end
 		else
 		begin
-			WB_En <= WB_En_in;
-			MEM_R_En <= MEM_R_En_in;
-			Is_Imm <= Is_Imm_in;
-			dest <= dest_in;
-			PC <= PC_in;
-			ALU_result <= ALU_result_in;
-			Mem_Data <= Mem_Data_in;
+			if (~stall) begin
+				WB_En <= WB_En_in;
+				MEM_R_En <= MEM_R_En_in;
+				Is_Imm <= Is_Imm_in;
+				dest <= dest_in;
+				PC <= PC_in;
+				ALU_result <= ALU_result_in;
+				Mem_Data <= Mem_Data_in;
+			end
 		end
 	end
-	
+
 endmodule

Sec_8/MIPS.v

@@ -13,13 +13,13 @@ module MIPS
 	);
 
 	// input and outputs
-	input			clk;
-	input			rst;
-	input			Sel;
-	output  	SRAMWEn;
-	output 		SRAMOE;
+	input					clk;
+	input					rst;
+	input					Sel;
+	output  			SRAMWEn;
+	output 				SRAMOE;
 	output [17:0]	SRAMaddress;
-	output	[5:0]	Instruction;
+	output [5:0]	Instruction;
 	inout	[15:0]	SRAMdata;
 
 	// wires
@@ -237,6 +237,7 @@ module MIPS
 		(
 			.clk(clk),
 			.rst(rst),
+			.stall(Stall),
 			.PC_in(PC2),
 			.PC(PC3),
 			.WB_En_in(WB_En22),
@@ -278,6 +279,7 @@ module MIPS
 		(
 			.clk(clk),
 			.rst(rst),
+			.stall(Stall),
 			.PC_in(PC3),
 			.PC(PC4),
 			.WB_En_in(WB_En32),

Sec_8/SRAM_CTR.v

@@ -34,7 +34,7 @@ module SRAM_CTR
 	localparam READ_2 = 2;
 	localparam WRITE_1 = 3;
 	localparam WAIT = 4;
-	
+
 	// wire and registers
 	reg 			SRAMWEn;
 	reg				SRAMOE;
@@ -47,11 +47,11 @@ module SRAM_CTR
 	reg		[2:0]	nextState;
 	reg		[15:0]	readData_L;
 	reg		[15:0]	readData_H;
-	
+
 	// build module
 	assign SRAM_NOT_READY = |counter | InnerStall;
 	assign readData = { readData_H, readData_L };
-	
+
 	always @(posedge clk) begin
 		if (rst)
 		begin
@@ -85,7 +85,7 @@ module SRAM_CTR
 			end
 		end
 	end
-	
+
 	// controller
 	always @( posedge clk )
 	begin
@@ -94,7 +94,7 @@ module SRAM_CTR
 		else
 			presentState <= nextState;
 	end
-	
+
 	always @(*) begin
 		case (presentState)
 			INIT:
@@ -135,11 +135,10 @@ module SRAM_CTR
 				end
 		endcase
 	end
-	
+
 	reg [15:0] data_to_sram;
 	always @( * )
 	begin
-	data_to_sram = 0;
 		case( presentState )
 			INIT:
 			begin
@@ -150,6 +149,7 @@ module SRAM_CTR
 					InnerStall = 1'b1;
 					SRAMWEn = 1'b1;
 					SRAMOE = 1'b0;
+					data_to_sram = 0;
 				end
 				else
 				begin
@@ -165,6 +165,7 @@ module SRAM_CTR
 						InnerStall = 1'b0;
 						SRAMWEn = 1'b1;
 						SRAMOE = 1'b1;
+						data_to_sram = 0;
 					end
 				end
 			end
@@ -174,13 +175,15 @@ module SRAM_CTR
 				InnerStall = 1'b0;
 				SRAMWEn = 1'b1;
 				SRAMOE = 1'b0;
+				data_to_sram = 0;
 			end
 			READ_2:
 			begin
 				SRAMaddress = { 1'b0, address, 1'b1 };
 				InnerStall = 1'b0;
 				SRAMWEn = 1'b1;
 				SRAMOE = 1'b1;
+				data_to_sram = 0;
 			end
 			WRITE_1:
 			begin
@@ -196,11 +199,11 @@ module SRAM_CTR
 				InnerStall = 1'b0;
 				SRAMWEn = 1'b1;
 				SRAMOE = 1'b1;
+				data_to_sram = 0;
 			end
 		endcase
 	end
-	
-	assign SRAMdata = ((presentState == WRITE_1) || ((presentState == INIT) && (MEM_W_EN == 1))) ?  data_to_sram : {16{1'bz}} ; 
-	
-endmodule
 
+	assign SRAMdata = (~(|(presentState ^ WRITE_1)) || (~(|(presentState ^ INIT)) && (MEM_W_EN == 1))) ?  data_to_sram : {16{1'bz}} ;
+
+endmodule