@@ -5,7 +5,8 @@ module ForwardUnit
5
5
WB_En1,
6
6
WB_En2,
7
7
mem_W_En,
8
- MEM_R_En,
8
+ mem_R_En1,
9
+ mem_R_En2,
9
10
Is_Imm,
10
11
src1,
11
12
src2,
@@ -19,14 +20,16 @@ module ForwardUnit
19
20
memOut,
20
21
shouldForward1,
21
22
shouldForward2,
23
+ loadForwardStall
22
24
);
23
25
24
26
// define input and output ports
25
27
input WB_En1;
26
28
input WB_En2;
27
29
input Is_Imm;
28
30
input mem_W_En;
29
- input mem_R_En;
31
+ input mem_R_En1;
32
+ input mem_R_En2;
30
33
input [1 :0 ] BR_Type;
31
34
input [4 :0 ] src1;
32
35
input [4 :0 ] src2;
@@ -47,8 +50,12 @@ module ForwardUnit
47
50
wire shouldForward2FromExe;
48
51
wire shouldForward1FromMem;
49
52
wire shouldForward2FromMem;
50
- wire shouldForwardMemWriteFromExe;
51
- wire shouldForwardMemWriteFromMem;
53
+ wire shouldForwardMemWriteFromExe;
54
+ wire shouldForwardMemWriteFromMem;
55
+ wire shouldForward1FromMemLoadExe; // depends on ld result
56
+ wire shouldForward2FromMemLoadExe;
57
+ wire shouldForward1FromMemLoadMem;
58
+ wire shouldForward2FromMemLoadMem;
52
59
reg [31 :0 ] srcOut1;
53
60
reg [31 :0 ] srcOut2;
54
61
reg [31 :0 ] memOut;
@@ -68,7 +75,14 @@ module ForwardUnit
68
75
assign shouldForward1 = shouldForward1FromExe | shouldForward1FromMem;
69
76
assign shouldForward2 = shouldForward2FromExe | shouldForward2FromMem;
70
77
71
- assign loadForwardStall = ! ( src2 ^ dest1 ) & WB_En1 & mem_R_En & | dest1;
78
+ // assign shouldForward1FromMemLoadExe = !( src1 ^ dest1 ) & mem_R_En1 & |dest1;
79
+ // assign shouldForward2FromMemLoadExe = !( src2 ^ dest1 ) & mem_R_En1 & |dest1;
80
+ assign shouldForward1FromMemLoadMem = ! ( src1 ^ dest2 ) & mem_R_En2 & | dest2;
81
+ assign shouldForward2FromMemLoadMem = ! ( src2 ^ dest2 ) & mem_R_En2 & | dest2;
82
+
83
+ assign loadForwardStall =
84
+ // (shouldForward1FromMemLoadExe | shouldForward2FromMemLoadExe) |
85
+ (shouldForward1FromMemLoadMem | shouldForward2FromMemLoadMem);
72
86
// build module
73
87
always @(* )
74
88
begin
0 commit comments