Fix double stalling in IF and ID

Author: mr-bat

Sec_8/ID_Reg.v

@@ -118,7 +118,7 @@ module ID_Stage_reg
 		end
 		else
 		begin
-			if (~stall | ~superStall)
+			if (~stall & ~superStall)
 			begin
 				dest <= dest_in;
 				readdata1 <= readdata1_in;

Sec_8/IF.v

@@ -4,6 +4,7 @@ module IF_Stage
 		clk,
 		rst,
 		stall,
+		superStall,
 		Instruction,
 		branch_taken,
 		branch_address,
@@ -14,6 +15,7 @@ module IF_Stage
 	input			clk;
 	input			rst;
 	input			stall;
+	input 		superStall;
 	input 			branch_taken;
 	input	[31:0]	branch_address;
 	output	[31:0]	Instruction;
@@ -35,7 +37,7 @@ module IF_Stage
 			if(branch_taken)
 					PC <= branch_address;
 			else
-				if( !stall )
+				if( ~stall & ~superStall )
 					PC <= PC + 4;
 		end
 	end
@@ -71,26 +73,26 @@ module IF_Stage
 		25:		Instruction = 32'b100100_00001_01011_00000_00000000100;//-- ld r11 ,r1 ,4//r11=-1456
 		26:		Instruction = 32'b100101_00001_01011_00000_00000011000;//-- st r11 ,r1 ,24
 		27:		Instruction = 32'b100101_00001_01001_00000_00000011100;//-- st r9 ,r1 ,28
-		28:		Instruction = 32'b100101_00001_01010_00000_00000100000;//-- st r10 ,r1 ,32 
+		28:		Instruction = 32'b100101_00001_01010_00000_00000100000;//-- st r10 ,r1 ,32
 		29:		Instruction = 32'b100101_00001_01000_00000_00000100100;//-- st r8 ,r1 ,36
 		30:		Instruction = 32'b100000_00000_00001_00000_00000000011;//-- Addi r1 ,r0 ,3 //r1=3
-		31:		Instruction = 32'b100000_00000_00100_00000_10000000000;//-- Addi r4 ,r0 ,1024   //r4=1024 
+		31:		Instruction = 32'b100000_00000_00100_00000_10000000000;//-- Addi r4 ,r0 ,1024   //r4=1024
 		32:		Instruction = 32'b100000_00000_00010_00000_00000000000;//-- Addi r2 ,r0 ,0 //r2=0
 		33:		Instruction = 32'b100000_00000_00011_00000_00000000001;//-- Addi r3 ,r0 ,1 //r3=1
 		34:		Instruction = 32'b100000_00000_01001_00000_00000000010;//-- Addi r9 ,r0 ,2 //r9=2
 		35:		Instruction = 32'b001010_00011_01001_01000_00000000000;//-- sll r8 ,r3 ,r9 //r8=r3*4
 		36:		Instruction = 32'b000001_00100_01000_01000_00000000000;//-- Add r8 ,r4 ,r8 //r8=1024+r3*4
 		37:		Instruction = 32'b100100_01000_00101_00000_00000000000;//-- ld r5 ,r8 ,0 //
 		38:		Instruction = 32'b100100_01000_00110_11111_11111111100;//-- ld r6 ,r8 ,-4 //
-		39:		Instruction = 32'b000011_00101_00110_01001_00000000000;//-- sub r9 ,r5 ,r6 
+		39:		Instruction = 32'b000011_00101_00110_01001_00000000000;//-- sub r9 ,r5 ,r6
 		40:		Instruction = 32'b100000_00000_01010_10000_00000000000;//-- Addi r10 ,r0 ,0x8000
 		41:		Instruction = 32'b100000_00000_01011_00000_00000010000;//-- Addi r11 ,r0 ,16 // r11 = 16
-		42:		Instruction = 32'b001010_01010_01011_01010_00000000000;//-- sll r10 ,r10 ,r11 // r10 = 2147483648 
+		42:		Instruction = 32'b001010_01010_01011_01010_00000000000;//-- sll r10 ,r10 ,r11 // r10 = 2147483648
 		43:		Instruction = 32'b000101_01001_01010_01001_00000000000;//-- And r9 ,r9 ,r10 // if(r5>r6) r9=0 else r9=-2147483648
-		44:		Instruction = 32'b101000_01001_00000_00000_00000000010;//-- Bez r9 ,2 
-		45:		Instruction = 32'b100101_01000_00101_11111_11111111100;//-- st r5 ,r8 ,-4 
+		44:		Instruction = 32'b101000_01001_00000_00000_00000000010;//-- Bez r9 ,2
+		45:		Instruction = 32'b100101_01000_00101_11111_11111111100;//-- st r5 ,r8 ,-4
 		46:		Instruction = 32'b100101_01000_00110_00000_00000000000;//-- st r6 ,r8 ,0
-		47:		Instruction = 32'b100000_00011_00011_00000_00000000001;//-- Addi r3 ,r3 ,1 // 
+		47:		Instruction = 32'b100000_00011_00011_00000_00000000001;//-- Addi r3 ,r3 ,1 //
 		48:		Instruction = 32'b101001_00001_00011_11111_11111110001;//-- BNE r1 ,r3 ,-15
 		49:		Instruction = 32'b100000_00010_00010_00000_00000000001;//-- Addi r2 ,r2 ,1 //2
 		50:		Instruction = 32'b101001_00001_00010_11111_11111101110;//-- BNE r1 ,r2 ,-18

Sec_8/IF_Reg.v

@@ -40,7 +40,7 @@ module IF_Stage_reg
 		end
 		else
 		begin
-			if( ~stall | ~superStall )
+			if( ~stall & ~superStall )
 			begin
 				Instruction <= Instruction_in;
 				PC <= PC_in;

Sec_8/MIPS.v

@@ -99,6 +99,7 @@ module MIPS
 			.clk(clk),
 			.rst(rst),
 			.stall(Stall),
+			.superStall(superStall),
 			.branch_address(Branch_Address),
 			.Instruction(Instruction1),
 			.branch_taken(Branch_Taken),