Stall for 5 cycles

Author: mr-bat

Sec_8/ForwardUnit.v

@@ -5,8 +5,6 @@ module ForwardUnit
 		WB_En1,
 		WB_En2,
 		mem_W_En,
-		//Is_Imm1,
-		//Is_Imm2,
 		Is_Imm,
 		src1,
 		src2,
@@ -53,19 +51,19 @@ module ForwardUnit
 	reg	[31:0]	memOut;
 
 	// define branch types
-	parameter NO_BRANCH_Code = 2'b0;
-	parameter BEZ_Code = 2'b01;
-	parameter BNE_Code = 2'b10;
-	parameter JMP_Code = 2'b11;
+	localparam NO_BRANCH_Code = 2'b0;
+	localparam BEZ_Code = 2'b01;
+	localparam BNE_Code = 2'b10;
+	localparam JMP_Code = 2'b11;
 
-    assign shouldForward1FromExe = !( src1 ^ dest1 ) & WB_En1 & |dest1;
-    assign shouldForward2FromExe = !( src2 ^ dest1 ) & WB_En1 & (~Is_Imm | !(BR_Type ^ BNE_Code)) & |dest1;
-    assign shouldForwardMemFromExe = !( src2 ^ dest1 ) & WB_En1 & mem_W_En  & |dest1;
-    assign shouldForward1FromMem = !( src1 ^ dest2 ) & WB_En2 & |dest2;
-    assign shouldForward2FromMem = !( src2 ^ dest2 ) & WB_En2 & (~Is_Imm | !(BR_Type ^ BNE_Code)) & |dest2;
-    assign shouldForwardMemFromMem = !( src2 ^ dest2 ) & WB_En2 & mem_W_En & |dest2;
-    assign shouldForward1 = shouldForward1FromExe | shouldForward1FromMem;
-    assign shouldForward2 = shouldForward2FromExe | shouldForward2FromMem;
+  assign shouldForward1FromExe = !( src1 ^ dest1 ) & WB_En1 & |dest1;
+  assign shouldForward2FromExe = !( src2 ^ dest1 ) & WB_En1 & (~Is_Imm | !(BR_Type ^ BNE_Code)) & |dest1;
+  assign shouldForwardMemFromExe = !( src2 ^ dest1 ) & WB_En1 & mem_W_En  & |dest1;
+  assign shouldForward1FromMem = !( src1 ^ dest2 ) & WB_En2 & |dest2;
+  assign shouldForward2FromMem = !( src2 ^ dest2 ) & WB_En2 & (~Is_Imm | !(BR_Type ^ BNE_Code)) & |dest2;
+  assign shouldForwardMemFromMem = !( src2 ^ dest2 ) & WB_En2 & mem_W_En & |dest2;
+  assign shouldForward1 = shouldForward1FromExe | shouldForward1FromMem;
+  assign shouldForward2 = shouldForward2FromExe | shouldForward2FromMem;
 	// build module
 	always @(*)
 	begin

Sec_8/SRAM_CTR.v

@@ -22,7 +22,7 @@ module SRAM_CTR
 	output 			SRAMWEn;
 	output			SRAMOE;
 	output	[17:0]	SRAMaddress;
-	output	[31:0]	writeData;
+	input	[31:0]	writeData;
 	input	[15:0]	address;
 	output			SRAM_NOT_READY;
 	output	[31:0]	readData;
@@ -39,7 +39,6 @@ module SRAM_CTR
 	reg 			SRAMWEn;
 	reg				SRAMOE;
 	reg		[17:0]	SRAMaddress;
-	reg		[31:0]	writeData;
 
 	reg				InnerStall;
 	reg 	[2:0] 	counter;
@@ -77,7 +76,7 @@ module SRAM_CTR
 		begin
 			if( InnerStall )
 			begin
-				counter <= 3'h6;
+				counter <= 3'h5;
 			end
 			if( ~InnerStall & |counter )
 			begin