ironside tdd service #2938
ironside tdd service #2938
Conversation
| __constant U32 _CORESIGHT_CLAIMSET_OFFSET = 0xFA0; | ||
| __constant U32 _CORESIGHT_CLAIMCLR_OFFSET = 0xFA4; |
There was a problem hiding this comment.
This usage of the CLAIM register is not standardized, but instead a bespoke solution that we made. Should we leave CLAIM configuration out here? It could always be added later if necessary.
There was a problem hiding this comment.
Given this is in a nordic specific file I feel this is ok, we aren't providing a general jlink script to configure coresight peripherals here
karstenkoenig
force-pushed
the
ironside_tdd
branch
3 times, most recently
from
9b827dd to
079ffa6
Compare
| #if defined(CONFIG_SOC_NRF54H20_ENABLE_TDD) | ||
| int err_tdd; | ||
|
|
||
| err_tdd = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT); |
There was a problem hiding this comment.
Should this also be invoked by PM state changes, if I'm not misunderstanding?
There was a problem hiding this comment.
In a final solution it can be, right now this will just force on tdd and leave it at that, hence preventing having to reconfigure all the coresight peripherals after a sleep etc, because JLink couldn't handle this.
This can be done when we have the coresight peripherals controlled from the application core but that'll need more time while this allows ETM over TPIU as a static state and is useful like this as is, just not power efficient
karstenkoenig
force-pushed
the
ironside_tdd
branch
4 times, most recently
from
ce33c40 to
d8082ca
Compare
karstenkoenig
force-pushed
the
ironside_tdd
branch
5 times, most recently
from
e51d881 to
d89da5d
Compare
karstenkoenig
force-pushed
the
ironside_tdd
branch
from
d89da5d to
ac03d99
Compare
|
@57300 I dropped the JLink change as we can pull this into a designated commit and PR to enable ETM |
karstenkoenig
force-pushed
the
ironside_tdd
branch
from
ac03d99 to
95d6e70
Compare
karstenkoenig
force-pushed
the
ironside_tdd
branch
from
95d6e70 to
15a91bd
Compare
karstenkoenig
force-pushed
the
ironside_tdd
branch
from
4fd8117 to
1544533
Compare
karstenkoenig
force-pushed
the
ironside_tdd
branch
2 times, most recently
from
aa1bee3 to
2976389
Compare
karstenkoenig
force-pushed
the
ironside_tdd
branch
from
2976389 to
062acd8
Compare
|
@nordicjm upstream CI is green after cherry-picking a fix from a different PR, so added this here as well. Can you please check again? You will notice a [noup] commit, sadly this can't be done upstream yet as it can go on relies on two different upstream PRs and hence doesn't have a place upstream, we can only do this after those get merged after the feature PRs are allowed again. I opened NCSDK-34289 against myself to follow up on this commit |
Added support for the IronSide TDD service which allows configuring and powering the trace and debug domain of the nrf54h20. Also provide option to start the trace and debug domain in the soc start sequence. Upstream PR #: 92340 Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Added support for ETM tracing via TPIU to the JLinkScript. Upstream PR #: 92340 Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
karstenkoenig
force-pushed
the
ironside_tdd
branch
from
062acd8 to
b1018d6
Compare
Configure the CTRLSET value and the clock pin so that the TRACE pins work when the TDD gets used. Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
|
Added support for the IronSide TDD service which allows configuring and
powering the trace and debug domain of the nrf54h20.
Also provide option to start the trace and debug domain in the soc start
sequence.