-
Notifications
You must be signed in to change notification settings - Fork 235
/
Copy pathinterrupts-hitachi-sh.h
executable file
·238 lines (197 loc) · 6.12 KB
/
interrupts-hitachi-sh.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
/*
Copyright (c) 1999-2008, Phillip Stanley-Marbell (author)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
* Redistributions of source code must retain the above
copyright notice, this list of conditions and the following
disclaimer.
* Redistributions in binary form must reproduce the above
copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials
provided with the distribution.
* Neither the name of the author nor the names of its
contributors may be used to endorse or promote products
derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
enum
{
/* Official SH3 exception codes */
POWER_ON_RESET_EXCP_CODE = 0x000,
H_UDI_RESET_EXCP_CODE = 0x000,
MANUAL_RESET_EXCP_CODE = 0x020,
TLB_LOAD_MISS_EXCP_CODE = 0x040,
TLB_LOAD_INVALID_EXCP_CODE = 0x040,
TLB_STORE_MISS_EXCP_CODE = 0x060,
TLB_STORE_INVALID_EXCP_CODE = 0x060,
TLB_INIT_PAGEWRITE_EXCP_CODE = 0x080,
TLB_LOAD_PROTECT_EXCP_CODE = 0x0A0,
TLB_STORE_PROTECT_EXCP_CODE = 0x0C0,
CPU_LOAD_ADDRERR_EXCP_CODE = 0x0E0,
CPU_STORE_ADDRERR_EXCP_CODE = 0x100,
TRAPA_EXCP_CODE = 0x160,
ILLEGAL_INSTR_EXCP_CODE = 0x180,
ILLEGAL_SLOT_INSTR_EXCP_CODE = 0x1A0,
USER_BKPOINT_TRAP_EXCP_CODE = 0x1E0,
DMA_ADDRERR_EXCP_CODE = 0x5C0,
/* Official SH3 interrupt code */
NMI_INTR_CODE = 0x1C0,
H_UDI_INTR_CODE = 0x5E0,
IRL3_IRL0_0000_INTR_CODE = 0x200,
IRL3_IRL0_0001_INTR_CODE = 0x220,
IRL3_IRL0_0010_INTR_CODE = 0x240,
IRL3_IRL0_0011_INTR_CODE = 0x260,
IRL3_IRL0_0100_INTR_CODE = 0x280,
IRL3_IRL0_0101_INTR_CODE = 0x2A0,
IRL3_IRL0_0110_INTR_CODE = 0x2C0,
IRL3_IRL0_0111_INTR_CODE = 0x2E0,
IRL3_IRL0_1000_INTR_CODE = 0x300,
IRL3_IRL0_1001_INTR_CODE = 0x320,
IRL3_IRL0_1010_INTR_CODE = 0x340,
IRL3_IRL0_1011_INTR_CODE = 0x360,
IRL3_IRL0_1100_INTR_CODE = 0x380,
IRL3_IRL0_1101_INTR_CODE = 0x3A0,
IRL3_IRL0_1110_INTR_CODE = 0x3C0,
/* Officially reserved exception codes */
RSV_CODE_1 = 0x120,
RSV_CODE_2 = 0x140,
RSV_CODE_3 = 0x3E0,
/* See network.h for why 0x5B2 */
BATT_LOW_EXCP_CODE = 0x5B2,
/* For now, battery IRQ is 14 */
BATT_LOW_FIXED_INTRLEVEL = 14,
NODEFAULT_EXCP_CODE = 0x5B5,
/* */
/* These codes are spaced so to permit */
/* 4096 NICs per device, with the code */
/* for NIC n being the value + n */
/* */
NIC_CODE_BEGIN = 0x1000,
NIC_RX_EXCP_CODE = 0x1000,
NIC_RX_EXCP_CODE_END = 0x2000,
NIC_TX_EXCP_CODE = 0x2000,
NIC_TX_EXCP_CODE_END = 0x3000,
NIC_ADDR_EXCP_CODE = 0x3000,
NIC_ADDR_EXCP_CODE_END = 0x4000,
NIC_FRAME_EXCP_CODE = 0x4000,
NIC_FRAME_EXCP_CODE_END = 0x5000,
NIC_COLLS_EXCP_CODE = 0x5000,
NIC_COLLS_EXCP_CODE_END = 0x6000,
NIC_CSENSE_EXCP_CODE = 0x6000,
NIC_CSENSE_EXCP_CODE_END = 0x7000,
NIC_RXOVRRUN_EXCP_CODE = 0x7000,
NIC_RXOVRRUN_EXCP_CODE_END = 0x8000,
NIC_RXUNDRRUN_EXCP_CODE = 0x8000,
NIC_RXUNDRRUN_EXCP_CODE_END = 0x9000,
NIC_TXOVRRUN_EXCP_CODE = 0x9000,
NIC_TXOVRRUN_EXCP_CODE_END = 0xA000,
NIC_TXUNDRRUN_EXCP_CODE = 0xA000,
NIC_TXUNDRRUN_EXCP_CODE_END = 0xB000,
NIC_CSUM_EXCP_CODE = 0xB000,
NIC_CSUM_EXCP_CODE_END = 0xC000,
NIC_CODE_END = 0xC000,
NIC_FIXED_INTRLEVEL = 15,
TMU0_TUNI0_EXCP_CODE = 0x400,
TMU1_TUNI1_EXCP_CODE = 0x420,
TMU2_TUNI2_EXCP_CODE = 0x440,
TMU0_TICPI2_EXCP_CODE = 0x460,
/* Fixed level for Dale */
TIMER_FIXED_INTRLEVEL = 15,
};
/* */
/* Unique exception types. This is useful for */
/* differentiation, since some exceptions share */
/* the same EXCP_CODE. */
/* */
enum
{
POWER_ON_RESET_EXCP,
H_UDI_RESET_EXCP,
MANUAL_RESET_EXCP,
TLB_LOAD_MISS_EXCP,
TLB_LOAD_INVALID_EXCP,
TLB_STORE_MISS_EXCP,
TLB_STORE_INVALID_EXCP,
TLB_INIT_PAGEWRITE_EXCP,
TLB_LOAD_PROTECT_EXCP,
TLB_STORE_PROTECT_EXCP,
CPU_LOAD_ADDRERR_EXCP,
CPU_STORE_ADDRERR_EXCP,
TRAPA_EXCP,
ILLEGAL_INSTR_EXCP,
ILLEGAL_SLOT_INSTR_EXCP,
USER_BKPOINT_TRAP_EXCP,
DMA_ADDRERR_EXCP,
NMI_INTR,
H_UDI_INTR,
IRL3_IRL0_0000_INTR,
IRL3_IRL0_0001_INTR,
IRL3_IRL0_0010_INTR,
IRL3_IRL0_0011_INTR,
IRL3_IRL0_0100_INTR,
IRL3_IRL0_0101_INTR,
IRL3_IRL0_0110_INTR,
IRL3_IRL0_0111_INTR,
IRL3_IRL0_1000_INTR,
IRL3_IRL0_1001_INTR,
IRL3_IRL0_1010_INTR,
IRL3_IRL0_1011_INTR,
IRL3_IRL0_1100_INTR,
IRL3_IRL0_1101_INTR,
IRL3_IRL0_1110_INTR,
BATT_LOW_INTR,
NODEFAULT_INTR,
/* */
/* Be sure to update dev7708.c and similar places */
/* if you add to, or remove items from here (for the */
/* correct clearing of NIC interrupts via NIC_NCR). */
/* */
NIC_RXOK_INTR,
NIC_TXOK_INTR,
NIC_ADDRERR_INTR,
NIC_FRAMEERR_INTR,
NIC_COLLSERR_INTR,
NIC_CSENSEERR_INTR,
NIC_RXOVRRUNERR_INTR,
NIC_RXUNDRRUNERR_INTR,
NIC_TXOVRRUNERR_INTR,
NIC_TXUNDRRUNERR_INTR,
NIC_CSUMERR_INTR,
};
/* Official Vector offsets */
enum
{
CPU_ADDRERR_OFFSET = 0x00000100,
CPU_INSTR_ADDRERR_OFFSET = 0x00000100,
DMA_ADDRERR_OFFSET = 0x00000100,
ILLEGAL_INSTR_OFFSET = 0x00000100,
ILLEGAL_SLOT_INSTR_OFFSET = 0x00000100,
TLB_INIT_PAGEWRITE_OFFSET = 0x00000100,
TLB_INVALID_OFFSET = 0x00000100,
TLB_MISS_OFFSET = 0x00000400,
TLB_PROTECT_OFFSET = 0x00000100,
TRAPA_OFFSET = 0x00000100,
USER_BKPOINT_OFFSET = 0x00000100,
NMI_OFFSET = 0x00000600,
EXT_HW_OFFSET = 0x00000600,
H_UDI_OFFSET = 0x00000600,
};
/* Fixed vector addresses */
enum
{
RESET_VECTOR_ADDR = 0xA0000000,
};