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op-riscv.c
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/*
Copyright (c) 2017-2018, Zhengyang Gu (author)
2019, Hein Alexander Mante (taint propagation)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
* Redistributions of source code must retain the above
copyright notice, this list of conditions and the following
disclaimer.
* Redistributions in binary form must reproduce the above
copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials
provided with the distribution.
* Neither the name of the author nor the names of its
contributors may be used to endorse or promote products
derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include "sf.h"
#include "instr-riscv.h"
#include "mextern.h"
uint32_t
sign_extend(uint32_t data, uint8_t n)
{
uint32_t sign_mask = 1 << (n-1);
uint32_t valid_bits;
if (n == 32)
{
valid_bits = -1;
}
else
{
valid_bits = (1 << n) - 1;
}
if (data & sign_mask)
{
return (data | (uint32_t) (-1 - valid_bits));
}
else
{
return (data & valid_bits);
}
}
/*
* Convert a 32 bit (single precision) float into a NaN 64 bit
* (double precision) float containing the single precision
* float in the lower 32 bits.
*/
uint64_t
nan_box(uint32_t f)
{
return ((~(uint64_t)0) << 32) | f;
}
/*
* Checks if a 64-bit value is NaN-boxed
* returns the lower 32-bits if NaN-boxed and a canonical NaN if otherwise
*/
uint32_t
is_nan_boxed(uint64_t f)
{
if((uint32_t)(f >> 32) == 0xFFFFFFFF) return (uint32_t)f;
else return 0x7FFFFFFF;
}
void
riscv_nop(Engine *E, State *S)/* pseudo instruction */
{
riscv_addi(E, S, 0, 0, 0);
return;
}
int get_uncertain_memory_index(Engine *E, State *S, uint32_t vaddr)
{
/* TODO: programmatically pick a sensible value
* Note that in the "finished" version uncertain memory will be
* indexed starting at zero and so this will not be needed.
*/
const uint32_t INST_END_ADDR = 0x8009fa4;
if ((vaddr & 0b11) != 0)
{
merror(E, "Unaligned uncertain aware floating point load/store at address 0x%08u", vaddr);
}
int addr = (int)(vaddr - INST_END_ADDR) / 4;
return addr;
}
void uncertain_check_part2_pc(Engine *E, State *S)
{
UncertainUpdateInfo *tmp = &S->riscv->uncertain->last_op;
if (tmp->op_fp_pc != S->riscv->P.EX.fetchedpc - 4)
{
merror(
E,
"Found second part of an uncertainty aware instruction that is not immediately proceded\n"
"in memory by a first part.\n"
"First part at 0x%08X and second part at 0x%08X.",
tmp->op_fp_pc,
S->riscv->P.EX.fetchedpc
);
}
}
void
riscv_add(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) + reg_read_riscv(E, S, rs2)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_sub(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) - reg_read_riscv(E, S, rs2)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_mul(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int64_t multiplicationResult=0;
int32_t resultLowerHalf=0;
/* --------- */
multiplicationResult = reg_read_riscv(E, S, rs1) * reg_read_riscv(E, S, rs2);
resultLowerHalf = multiplicationResult & 0xFFFFFFFF;
if (multiplicationResult < 0)
{
resultLowerHalf = -resultLowerHalf;
}
reg_set_riscv(E, S, rd, resultLowerHalf);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_mulh(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int64_t multiplicationResult=0;
int32_t resultLowerHalf=0;
multiplicationResult = reg_read_riscv(E, S, rs1) * reg_read_riscv(E, S, rs2);
resultLowerHalf = (multiplicationResult >> 32) & 0xFFFFFFFF;
reg_set_riscv(E, S, rd, resultLowerHalf);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_mulhu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
uint64_t multiplicationResult=0;
uint32_t resultLowerHalf=0;
multiplicationResult = reg_read_riscv(E, S, rs1) * reg_read_riscv(E, S, rs2);
resultLowerHalf = (multiplicationResult >> 32) & 0xFFFFFFFF;
reg_set_riscv(E, S, rd, resultLowerHalf);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_mulhsu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int64_t multiplicationResult=0;
int32_t resultLowerHalf=0;
multiplicationResult = reg_read_riscv(E, S, rs1) * reg_read_riscv(E, S, rs2);
resultLowerHalf = (multiplicationResult >> 32) & 0xFFFFFFFF;
reg_set_riscv(E, S, rd, resultLowerHalf);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_div(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int32_t dividend, divisor, quotient;
dividend = (int32_t) reg_read_riscv(E, S, rs1);
divisor = (int32_t) reg_read_riscv(E, S, rs2);
if (divisor != 0)
{
quotient = dividend / divisor;
}
else /* Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified - page 44 */
{
quotient = -1;
}
reg_set_riscv(E, S, rd, quotient);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_divu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
uint32_t dividend, divisor, quotient;
dividend = reg_read_riscv(E, S, rs1);
divisor = reg_read_riscv(E, S, rs2);
if (divisor != 0)
{
quotient = dividend / divisor;
}
else /* Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified - page 44 */
{
quotient = 0xFFFFFFFF;
}
//fprintf(stderr, "riscv_divu: rs2 %d. rs1 %d. Rd is %d.\n", rs2, rs1, rd);
//fprintf(stderr, "riscv_divu: dividend: %d. divisor: %d. quotient: %d.\n", dividend, divisor, quotient);
reg_set_riscv(E, S, rd, quotient);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_rem(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int32_t dividend, divisor, remainder;
dividend = (int32_t) reg_read_riscv(E, S, rs1);
divisor = (int32_t) reg_read_riscv(E, S, rs2);
if (divisor != 0)
{
remainder = dividend % divisor;
}
else /* Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified - page 44 */
{
remainder = dividend;
}
reg_set_riscv(E, S, rd, remainder);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_remu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
uint32_t dividend, divisor, remainder;
dividend = reg_read_riscv(E, S, rs1);
divisor = reg_read_riscv(E, S, rs2);
if (divisor != 0)
{
remainder = dividend % divisor;
}
else /* Volume I: RISC-V Unprivileged ISA V20190608-Base-Ratified - page 44 */
{
remainder = dividend;
}
reg_set_riscv(E, S, rd, remainder);
if (SF_TAINTANALYSIS)
{
/* FIXME */
}
}
void
riscv_slt(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
if ((int32_t) reg_read_riscv(E, S, rs1) < (int32_t) reg_read_riscv(E, S, rs2))
{
reg_set_riscv(E, S, rd, 1);
}
else
{
reg_set_riscv(E, S, rd, 0);
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_sltu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
if (reg_read_riscv(E, S, rs1) < reg_read_riscv(E, S, rs2))
{
reg_set_riscv(E, S, rd, 1);
}
else
{
reg_set_riscv(E, S, rd, 0);
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_and(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) & reg_read_riscv(E, S, rs2)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_or(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) | reg_read_riscv(E, S, rs2)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_xor(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) ^ reg_read_riscv(E, S, rs2)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_sll(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int xlen_b = 5;
int mask = ((1 << xlen_b) - 1);
uint8_t shift = reg_read_riscv(E, S, rs2) & mask;
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) << shift));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_srl(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int xlen_b = 5;
int mask = ((1 << xlen_b) - 1);
uint8_t shift = reg_read_riscv(E, S, rs2) & mask;
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) >> shift));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_sra(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd)
{
int xlen_b = 5;
int mask = ((1 << xlen_b) - 1);
uint8_t shift = reg_read_riscv(E, S, rs2) & mask;
uint32_t data = ((signed int) reg_read_riscv(E, S, rs1)) >> shift;
reg_set_riscv(E, S, rd, data);
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_addi(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
/*
* Assumption: imm0 carries no taint (assumption carries on to all other functions
* with immediate values but will only be stated here)
*/
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) + (int32_t) sign_extend(imm0, 12)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_slti(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
if ((int32_t) reg_read_riscv(E, S, rs1) < (int32_t) sign_extend(imm0, 12))
{
reg_set_riscv(E, S, rd, 1);
}
else
{
reg_set_riscv(E, S, rd, 0);
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_sltiu(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
if (reg_read_riscv(E, S, rs1) < sign_extend(imm0, 12))
{
reg_set_riscv(E, S, rd, 1);
}
else
{
reg_set_riscv(E, S, rd, 0);
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_andi(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) & sign_extend(imm0, 12)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_ori(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) | sign_extend(imm0, 12)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_xori(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) ^ sign_extend(imm0, 12)));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_slli(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
int xlen_b = 5;
int mask = ((1 << xlen_b) - 1);
uint8_t shift = imm0 & mask;
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) << shift));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_srli(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
int xlen_b = 5;
int mask = ((1 << xlen_b) - 1);
uint8_t shift = imm0 & mask;
reg_set_riscv(E, S, rd, (reg_read_riscv(E, S, rs1) >> shift));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_srai(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint32_t imm0)
{
int xlen_b = 5;
int mask = ((1 << xlen_b) - 1);
uint8_t shift = imm0 & mask;
uint32_t data = ((signed int)reg_read_riscv(E, S, rs1)) >> shift;
reg_set_riscv(E, S, rd, data);
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_lui(Engine *E, State *S, uint8_t rd, uint32_t imm0)
{
reg_set_riscv(E, S, rd, (imm0<<12));
return;
}
void
riscv_auipc(Engine *E, State *S, uint8_t rd, uint32_t imm0)
{
reg_set_riscv(E, S, rd, (imm0<<12) + S->PC - 4);
if (SF_TAINTANALYSIS)
{
/*
* Propagate taint of PC into register[rd]:
*/
taintprop(E, S, taintretreg(E,S,32), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_jal(Engine *E, State *S, uint8_t rd, uint16_t imm1, uint8_t imm11, uint8_t imm12, uint8_t imm20)
{
int32_t offset = sign_extend((imm1 << 1) + (imm11 << 11) + (imm12 << 12) + (imm20 << 20), 21);
reg_set_riscv(E, S, rd, S->PC);
S->PC += offset - 4;
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,32), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
/*
* If immediates are seen as carrying taint, more then their taint
* should also be propagated to the PC (ORed with the PC's previous
* taint).
*/
}
return;
}
void
riscv_jalr(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0)
{
int32_t addr = (int32_t) sign_extend(imm0, 12) + (int32_t) reg_read_riscv(E, S, rs1);
uint32_t mask = -2;
reg_set_riscv(E, S, rd, S->PC);
S->PC = (addr) & mask;
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,32), 0,
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
taintprop(E, S, taintretreg(E,S,rs1), 0,
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_beq(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t imm1, uint8_t imm5,\
uint8_t imm11, uint8_t imm12)
{
if (reg_read_riscv(E, S, rs1) == reg_read_riscv(E, S, rs2))
{
int32_t offset = sign_extend((imm1 << 1) + (imm5 << 5) + (imm11 << 11) \
+ (imm12 << 12), 13);
S->PC += offset - 4;
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_bne(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t imm1, uint8_t imm5,\
uint8_t imm11, uint8_t imm12)
{
if (reg_read_riscv(E, S, rs1) != reg_read_riscv(E, S, rs2))
{
int32_t offset = sign_extend((imm1 << 1) + (imm5 << 5) + (imm11 << 11) \
+ (imm12 << 12), 13);
S->PC += offset - 4;
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_blt(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t imm1, uint8_t imm5,\
uint8_t imm11, uint8_t imm12)
{
if ((int32_t) reg_read_riscv(E, S, rs1) < (int32_t) reg_read_riscv(E, S, rs2))
{
int32_t offset = sign_extend((imm1 << 1) + (imm5 << 5) + (imm11 << 11) \
+ (imm12 << 12), 13);
S->PC += offset - 4;
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_bltu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t imm1, uint8_t imm5,\
uint8_t imm11, uint8_t imm12)
{
if (reg_read_riscv(E, S, rs1) < reg_read_riscv(E, S, rs2))
{
int32_t offset = sign_extend((imm1 << 1) + (imm5 << 5) + (imm11 << 11) \
+ (imm12 << 12), 13);
S->PC += offset - 4;
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_bge(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t imm1, uint8_t imm5,\
uint8_t imm11, uint8_t imm12)
{
if ((int32_t) reg_read_riscv(E, S, rs1) >= (int32_t) reg_read_riscv(E, S, rs2))
{
int32_t offset = sign_extend((imm1 << 1) + (imm5 << 5) + (imm11 << 11) \
+ (imm12 << 12), 13);
S->PC += offset - 4;
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_bgeu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t imm1, uint8_t imm5,\
uint8_t imm11, uint8_t imm12)
{
if (reg_read_riscv(E, S, rs1) >= reg_read_riscv(E, S, rs2))
{
int32_t offset = sign_extend((imm1 << 1) + (imm5 << 5) + (imm11 << 11) \
+ (imm12 << 12), 13);
S->PC += offset - 4;
}
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)32, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_lw(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12);
uint32_t value = riscVreadlong(E, S, addr);
reg_set_riscv(E, S, rd, value);
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretmems(E,S,addr,4),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_lh(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12);
reg_set_riscv(E, S, rd, sign_extend(riscVreadword(E, S, addr), 16));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretmems(E,S,addr,2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_lhu(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12);
reg_set_riscv(E, S, rd, (uint32_t) riscVreadword(E, S, addr));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretmems(E,S,addr,2),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_lb(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12);
uint8_t data_b = riscVreadword(E, S, addr) & 0xff;
reg_set_riscv(E, S, rd, sign_extend(data_b, 8));
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretmems(E,S,addr,1),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_lbu(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12);
uint8_t data_b = riscVreadbyte(E, S, addr);
reg_set_riscv(E, S, rd, (uint32_t) data_b);
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretmems(E,S,addr,1),
(uint64_t)rd, kSunflowerTaintMemTypeRegister);
}
return;
}
void
riscv_sw(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t imm5)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0 + (imm5 << 5), 12);
uint32_t value = reg_read_riscv(E,S, rs2);
riscVwritelong(E, S, addr, value);
if (SF_TAINTANALYSIS)
{
for (int i = 0 ; i<4 ; i++)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)(addr+i), kSunflowerTaintMemTypeMemory);
}
}
}
void
riscv_sh(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t imm5)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0 + (imm5 << 5), 12);
riscVwriteword(E, S,addr, reg_read_riscv(E,S, rs2) & 0xffff);
if (SF_TAINTANALYSIS)
{
for (int i = 0 ; i<2 ; i++)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)(addr+i), kSunflowerTaintMemTypeMemory);
}
}
}
void
riscv_sb(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t imm5)
{
uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0 + (imm5 << 5), 12);
riscVwritebyte(E, S,addr, reg_read_riscv(E,S, rs2) & 0xff);
if (SF_TAINTANALYSIS)
{
taintprop(E, S, taintretreg(E,S,rs1), taintretreg(E,S,rs2),
(uint64_t)addr, kSunflowerTaintMemTypeMemory);
}
}
void
riscv_fence(Engine *E, State *S)
{
return;
}
void
riscv_fence_i(Engine *E, State *S)
{
return;
}
void
riscv_cor(Engine *E, State *S)
{
return;
}
void
riscv_ebreak(Engine *E, State *S)
{
return;
}
void
riscv_csrrw(Engine *E, State *S)
{
return;
}
void
riscv_csrrs(Engine *E, State *S)
{
return;
}
void
riscv_csrrc(Engine *E, State *S)
{
return;
}
void
riscv_csrrwi(Engine *E, State *S)
{