Convolutional-Neural-Network-hardware-using-Verilog

A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers. Sigmoid case statement was also implemented in verilog to get the sigmoid values for intermediate outputs in a layer. This design was simulated and synthesized at 50 MHz on Quartus Prime 17.0. The FPGA family was Cyclone V. Total logic elements used were 724, total bits used 121856(only 50% use of memory).