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  Welcome to verilog-ethernet Discussions!

  alexforencich started Dec 11, 2020 in General

  

  

  

  

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  2.5G and 5G Support?

  hopethis asked Jan 30, 2024 in Q&A · Unanswered

  

  

  

  

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  VCU108 Ethernet

  muhammedalfina asked Feb 13, 2025 in Q&A · Unanswered

  

  

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  Problem sending multiple packets back to back

  cube1us asked Feb 10, 2025 in Q&A · Closed · Unanswered

  

  

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  Testing

  kavyash15 asked Jan 3, 2025 in Q&A · Unanswered

  

  

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  Connection Problem in 10 Gbit UDP, IP and ARP Supported Design

  adnanakcan asked Dec 29, 2024 in Q&A · Unanswered

  

  

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  When I am trying this project in AX7203 board, it has KSZ9031RNX PHY, which requires typical 2.5MHz mdc clock and it has mdio interface to communicate with PHY. I am following the NexysVideo project for reference. It does not have mdio interface. I get some negative slack. How can I add MDIO to be able to talk to PHY and what commands should i send to configure PHY ?

  kavyash15 asked Dec 18, 2024 in Q&A · Unanswered

  

  

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  25G on Intel/Altera

  mshu-nw asked Dec 17, 2024 in Q&A · Unanswered

  

  

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  I am trying to replicate the project using AX7203 board with Artix-7 FPGA in it. It uses 200MHz differential clock. How to make MMCM module to take in differential clock and produce output ?

  kavyash15 asked Dec 16, 2024 in Q&A · Closed · Answered

  

  

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  Error in VCU108 fpga.xdc

  LuppiLup started Oct 23, 2024 in General

  

  

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  Verilog : It's supposed to be a MOD10 counter but it counts from 0 to 9 and resets to 4, why??

  Darokcamper asked Oct 21, 2024 in Q&A · Unanswered

  

  

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  Does this project support SGMII interface now?

  yinyeyy asked Nov 7, 2023 in Q&A · Unanswered

  

  

  

  

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  VCU118 minimal example for one SFP+ on HiTech Global HTG-FMC-X6QSFP28 FMC+

  dorotheapfeiffer asked Sep 18, 2024 in Q&A · Unanswered

  

  

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  HELP - just trying to send a UDP packet without recieving one first

  cube1us started Aug 4, 2024 in General

  

  

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  FYI: Adapted to Digilent Nexys4 with

  cube1us started Jul 23, 2024 in Show and tell

  

  

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  CRC 32 CALCULATION

  sallyakj asked Jul 3, 2024 in Q&A · Unanswered

  

  

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  Build option for all of the project

  sallyakj asked May 19, 2024 in Q&A · Unanswered

  

  

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  eth_mac_1g_gmii_fifo with Xilinx 1G/2.5G Ethernet PCS/PMA in 1000BASE-X mode

  tristancmorgan asked May 21, 2024 in Q&A · Unanswered

  

  

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  RGMII PHY with fixed link

  dorotheapfeiffer asked Apr 26, 2024 in Q&A · Closed · Answered

  

  

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  Changes to ip_eth_tx_64.v

  EdwinEstep asked Apr 29, 2024 in Q&A · Unanswered

  

  

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  How do I adapt rgmii_phy_if.v for use with Lattice ECP5 primitives for IODDR and Clock input style?

  t1ch asked Mar 24, 2024 in Q&A · Unanswered

  

  

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  eth_mac_phy_10g_fifo missing external serdes_rx_reset_req?

  rconraduw started Feb 23, 2023 in General

  

  

  

  

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  Sniffing UDP packets when phy is used by PS

  catkira asked Feb 15, 2024 in Q&A · Closed · Answered

  

  

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  X3 Port Request

  lotusdew1980 started Feb 19, 2024 in Ideas

  

  

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  ZCU106 example design test ,no data return

  JLFu asked Nov 29, 2023 in Q&A · Unanswered

  

  

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