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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 761 public repositories matching this topic...

monibuca

langhuihui / monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

rtsp hls livestream rtmp websocket webrtc flv ts rtp mediaserver hdl

Updated Jun 26, 2025
Go

neorv32

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga processor vhdl riscv smp multi-core rtos hdl soc risc-v soft-core system-on-chip rv32 asip neorv32 on-chip-debbuger

Updated Jun 22, 2025
VHDL

amaranth-lang / amaranth

A modern hardware definition language and toolchain based on Python

fpga hdl amaranth-hdl

Updated Jun 25, 2025
Python

analogdevicesinc / hdl

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Jun 26, 2025
Verilog

metroboy

aappleby / metroboy

A repository of gate-level simulators and tools for the original Game Boy.

emulator simulator gameboy gameboy-emulator verilog hdl

Updated Feb 23, 2025
C++

drom / awesome-hdl

Hardware Description Languages

awesome vhdl verilog awesome-list hdl hacktoberfest hardware-description-language

Updated Feb 7, 2025

veryl

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog hdl

Updated Jun 26, 2025
Rust

m-labs / nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga hdl yosys nmigen

Updated Jan 8, 2022
Python

WangXuan95 / BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

fpga verilog bluespec hdl bluespec-systemverilog bsv hardware-description-language

Updated Sep 15, 2023
Bluespec

intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

framework simulator hardware verification rtl hdl hardware-verification hardware-design

Updated Jun 25, 2025
Dart

Nuand / bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

vhdl rtl hdl ofdm bladerf ofdm-wireless-communications 80211 dsss

Updated Apr 15, 2024
VHDL

pymtl / pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

Updated May 4, 2025
Python

slaclab / surf

A huge VHDL library for FPGA and digital ASIC development

python asic fpga firmware vhdl hdl

Updated Jun 25, 2025
VHDL

tensil-ai / tensil

Open source machine learning accelerators

machine-learning scala asic fpga artificial-intelligence hdl silicon

Updated Mar 24, 2024
Scala

analogdevicesinc / plutosdr-fw

PlutoSDR Firmware

linux fpga sdr iio transceiver rf hdl plutosdr adalm-pluto active-learning-module plutosdr-fw plutosdr-firmware

Updated Oct 15, 2024
Shell

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

viduraakalanka / HDL-Bits-Solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

verilog hdl

Updated Jul 16, 2023
Verilog

sv-tests

chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

rtl verilog systemverilog hdl compliance-testing symbiflow

Updated Jun 26, 2025
SystemVerilog

spamegg1 / reviews

Reviewing some online CS courses I took

Updated Mar 10, 2025
JavaScript

Kitware / VeloView

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

lidar velodyne-sensor velodyne sensor-data hdl lidar-measurements lidar-data-manipulation lidar-camera-calibration velodyne-hdl-sensors sensor-streaming

Updated Sep 29, 2021
C++

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Website: github.com/topics/verilog
Wikipedia: Wikipedia