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[RISC-V] Need to configure target RISC-V extension for coreclr build #115296

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@fuad1502

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@fuad1502

There is a need to enable certain extensions for RISC-V coreclr builds. For example, emitLoadImmediate makes heavy use of bit count intrinsics.

void emitter::emitLoadImmediate(emitAttr size, regNumber reg, ssize_t imm)

We can increase the JIT throughput of this function by enabling Zbb extension. This is only one example where we could improve RISC-V JIT throughput by enabling certain extensions. Other extensions, such as Zba and Zicond can improve throughput at various places.

Currently, the compiler (clang) uses the default configuration for RISC-V target, which "only" enables the rv64gc "profile".

We can use CLR_ADDITIONAL_COMPILER_OPTIONS to pass in -march=rv64gc_zbb to clang:

if(CLR_CMAKE_HOST_UNIX)
add_compile_options(${CLR_ADDITIONAL_COMPILER_OPTIONS})
endif(CLR_CMAKE_HOST_UNIX)

But I was wondering if we should introduce a better way to enable these extensions, akin to what we have for ARM:

if(CLR_CMAKE_HOST_UNIX_ARM)
if (NOT DEFINED CLR_ARM_FPU_TYPE)
set(CLR_ARM_FPU_TYPE vfpv3)
endif(NOT DEFINED CLR_ARM_FPU_TYPE)

There are several alternative proposals that I would like to suggest:

  • Introduce RISCV_EXTENSIONS CMake option. User can pass in Zba_Zicond_....
  • Introduce RISCV_PROFILE CMake option. User can pass in rv22, rv23, etc.
  • Introduce options for each extension that might be useful, e.g. RISCV_ZBB=1, adding it only when a need arises.
  • Change the default profile to RVA20/22/23.

cc @dotnet/samsung

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    arch-riscvRelated to the RISC-V architecturearea-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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