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Arm64: Implement region write barriers #111636

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Merged
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May 17, 2025
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db6c2cf
Arm64: Implement region write barriers
a74nh Jan 16, 2025
5de7e0f
Fix byte region barriers
a74nh Jan 21, 2025
9315aa1
Fix bit region barriers
a74nh Jan 21, 2025
d0e46f0
test instead of cmp for bitwise write barriers
a74nh Jan 22, 2025
cb83f53
use LSE to atomically update bitwise write barriers
a74nh Jan 22, 2025
c615772
move atomics check into gcenv.ee.cpp
a74nh Jan 23, 2025
1c865f1
Skip ephemeral checks for regionless server GC, and refactor checks
a74nh Jan 23, 2025
15dde1b
Move ephemeral checks back
a74nh Jan 24, 2025
b5b28ce
Add GC-write-barriers.md
a74nh Jan 27, 2025
c27d516
More variables for the pseudo code
a74nh Jan 27, 2025
d014417
WRITE_BARRIER_CHECK instead of TARGET_ARM64
a74nh Jan 27, 2025
6068fb0
Add JIT_CheckedWriteBarrier and fixups to doc
a74nh Jan 28, 2025
fe0ab46
Merge main
a74nh Mar 4, 2025
a416437
Use writebarriermanager for arm64.
a74nh Jan 13, 2025
86c2576
Add the different write barrier functions
a74nh Feb 25, 2025
38bc2a1
Don't clear ephemeral values
a74nh Mar 4, 2025
5eed451
Only use offsets for inline variables
a74nh Mar 4, 2025
6b29574
Remove jitinterfaceamd64.cpp
a74nh Mar 4, 2025
e3bbf96
Don't use m_pRegionShrSrc on Arm64
a74nh Mar 4, 2025
091e265
Remove commented code
a74nh Mar 4, 2025
91eb26f
make writebarriermanager closer to original code
a74nh Mar 4, 2025
b947119
undo patchedcode.asm changes
a74nh Mar 4, 2025
580c16f
Add writebarriermanager.h
a74nh Mar 4, 2025
7993687
Update doc
a74nh Mar 5, 2025
90d889b
Replace JIT_WriteBarrier with zeroed memory
a74nh Mar 5, 2025
da7b5c0
Fix writebarrier macro labels
a74nh Mar 5, 2025
dc6d0a7
Fix JIT_WriteBarrier_PreGrow64 checks
a74nh Mar 5, 2025
6e66842
remove unused label
a74nh Mar 5, 2025
729cb77
Remove JIT_UpdateWriteBarrierState
a74nh Mar 5, 2025
e0759b8
first attempt at windows .asm
a74nh Mar 5, 2025
e026a06
remove wbs_begin
a74nh Mar 5, 2025
678f8e1
fix ifdefs for windows
a74nh Mar 7, 2025
5a156d3
Remove _TEXT
a74nh Mar 7, 2025
b318113
Fix macro arg passing on OSX
a74nh Mar 7, 2025
9312f3c
Fix patching arithmetic to work on MacOS
a74nh Mar 12, 2025
13bd03c
merge main
a74nh Mar 12, 2025
0f21673
Fixup comments in doc and assembly
a74nh Mar 13, 2025
48620bb
fix location casts for windows
a74nh Mar 13, 2025
d97e4c1
copy patching changes to windows
a74nh Mar 13, 2025
8f73468
fix location casts again
a74nh Mar 13, 2025
b5cbb9e
remove extra labels
a74nh Mar 14, 2025
4dc3f63
fix windows build
a74nh Mar 14, 2025
6ea99c0
fix patched constants on windows
a74nh Mar 14, 2025
75d2443
Fix RegionShr size on windows
a74nh Mar 19, 2025
08c3635
Merge main
a74nh Mar 19, 2025
1c80ab8
Merge main
a74nh Apr 7, 2025
aefc2ef
Add WRITE_BARRIER_CHECK and LSE atomics to the doc
a74nh Apr 15, 2025
8e0dbe4
merge main
a74nh Apr 17, 2025
8d164ef
doc typo fixes
a74nh Apr 22, 2025
8b02ab4
Merge main
a74nh Apr 22, 2025
328024e
Merge main
a74nh May 16, 2025
801b9cc
Merge main
a74nh May 16, 2025
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11 changes: 8 additions & 3 deletions docs/design/coreclr/jit/GC-write-barriers.md
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ JIT_WriteBarrier(Object **dst, Object *ref)
Set *dst = ref

// Shadow Heap update
ifdef WRITE_BARRIER_CHECK:
ifdef WRITE_BARRIER_CHECK: // Only set in DEBUG mode
if g_GCShadow != 0:
long *shadow_dst = g_GCShadow + (dst - g_lowest_address)
// Check shadow heap location is within shadow heap
Expand Down Expand Up @@ -89,8 +89,13 @@ JIT_CheckedWriteBarrier(Object **dst, Object *ref)
return JIT_WriteBarrier(dst, ref)
````

## WritebarrierManager

On AMD64 and Arm64, there several different implementations of the write barrier function. Each version is a subset of the `JIT_WriteBarrier` above, assuming different state, meaning most `if` checks can be skipped. The actual write barrier that is called is a copy of one of these implementations.

## WritebarrierManager
The WritebarrierManager keeps track of which implementation is currently being used. As internal state changes, the WritebarrierManager updates the copy to the correct implementation. In practice, most of the internal state is fixed on startup, with only changes to/from use of write watch barriers changing during runtime.

`WRITE_BARRIER_CHECK` is only set in `DEBUG` mode. On Arm64 `WRITE_BARRIER_CHECK` checks exist at the top of each version of the function when `DEBUG` mode is enabled. On `Amd64` these checks do not exist. Instead, a special `JIT_WriteBarrier_Debug` version of the function exists, which contains most of the functionality of `JIT_WriteBarrier` pseudo code and is used exclusively when `DEBUG` mode is enabled.

On Arm64, g_region_use_bitwise_write_barrier is only set if LSE atomics are present on the hardware, as only LSE provides an single instruction to atomically update a byte via a bitwise OR.

On AMD64 and Arm64, there several different implementations of the write barrier function. Each implementation assumes different state and so can skip certain checks. The actual write barrier that is called is a copy of one of these implementations. The WritebarrierManager keeps track of which implementation is currently being used. As internal state changes, the WritebarrierManager updates the copy to the correct implementation. In practice, most of the internal state is fixed on startup, with only changes to/from use of write watch barriers changing during runtime.
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