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Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

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BrianHGinc/Verilog-Floating-Point-Clock-Divider

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Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

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verilog verilog-hdl verilog-components clock-generator

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BHG_FP_CLK_DIVIDER_v1.3 Latest
Feb 3, 2025
+ 1 release

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