This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Assignment of Microelectronic Circuits using HSPICE to simulate some of CMOS gates logics.

Verification of D-FF using UVM on EDA playground

Verilog behavioral models of SR, D, JK, and T flip-flops with testbenches and simulation results.

Digital Circuits made with VHDL

The VHDL code describes a D flip-flop with synchronous reset functionality.

assignments on flipflop