[ImportVerilog] Cannot compile forward decleared string type

[Max-astro]

I want to support this sv-tests-results/string_concat_op feature, but not sure how to fix it properly.

module top();

string str;

initial begin
    str = "Hello";
end

endmodule

circt-verilog has the following complaints when compiling the string.sv file:

string str;
       ^
s.sv:3:8: note: see current operation: %0 = "moore.variable"() <{name = "str"}> : () -> !moore.ref<string>

This error is due to MooreToCore's lack of string-type conversion. It only has StringConstantOpConv and Format*OpConversion; none of these conversions can handle the string type.

[chenbo-again]

I found hw dialect has HWStringType, and maybe it's a proper target for lowering moore.string.

[fabianschuiki]

Thanks for working on this, @Max-astro! HW doesn't have very good string support -- it's limited mostly to fixed-sized strings or strings that can be passed to module instances as parameter. There has been a recent effort in the Sim dialect, which collects simulation-related things, to come up with ways to do string formatting and representing format string literals. I think the Sim dialect would be a great place to add a type for dynamic strings such as Verilog's string type, and also have operations like concatenation, casting, and indexing. Maybe that would be a way forward for you?

[Max-astro]

I think the Sim dialect would be a great place to add a type for dynamic strings such as Verilog's string type, and also have operations like concatenation, casting, and indexing.

Thank you for your advice, I'll take a look at the Sim dialect and see if it's easy to add a dynamic string type.