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tclin914circYuan
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DhruvSrivastavaX
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[RISCV] Implement intrinsics for XAndesVDot (llvm#141441)
This patch implements clang intrinsic support for XAndesVDot. The document for the intrinsics can be found at: https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#andes-vector-dot-product-extensionxandesvdot and with policy variants https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/policy_funcs/intrinsic_funcs.adoc#andes-vector-dot-product-extensionxandesvdot Co-authored-by: Tony Chuan-Yue Yuan <yuan593@andestech.com>
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‎clang/include/clang/Basic/riscv_andes_vector.td

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Original file line numberDiff line numberDiff line change
@@ -81,3 +81,24 @@ let ManualCodegen = [{
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defm nds_vfpmadb : RVVFPMAD;
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}
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}
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// Andes Vector Dot Product Extension (XAndesVDot)
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multiclass RVVD4DOT<list<list<string>> i_suffixes_prototypes,
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list<list<string>> l_suffixes_prototypes> {
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let RequiredFeatures = ["Xandesvdot"],
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UnMaskedPolicyScheme = HasPolicyOperand,
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HasMaskedOffOperand = false,
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Log2LMUL = [-1, 0, 1, 2, 3],
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OverloadedName = NAME in {
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defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "i", i_suffixes_prototypes>;
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defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "l", l_suffixes_prototypes>;
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}
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}
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defm nds_vd4dots : RVVD4DOT<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"]],
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[["vv", "v", "vv(FixedSEW:16)v(FixedSEW:16)v"]]>;
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defm nds_vd4dotu : RVVD4DOT<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"]],
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[["vv", "Uv", "UvUv(FixedSEW:16)Uv(FixedSEW:16)Uv"]]>;
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defm nds_vd4dotsu : RVVD4DOT<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"]],
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[["vv", "v", "vv(FixedSEW:16)v(FixedSEW:16)Uv"]]>;

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -489,6 +489,7 @@ class RVVIntrinsic {
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enum RVVRequire {
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RVV_REQ_RV64,
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RVV_REQ_Zvfhmin,
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RVV_REQ_Xandesvdot,
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RVV_REQ_Xandesvpackfph,
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RVV_REQ_Xsfvcp,
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RVV_REQ_Xsfvfnrclipxfqf,

‎clang/lib/Sema/SemaRISCV.cpp

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@@ -225,6 +225,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
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const TargetInfo &TI = Context.getTargetInfo();
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static const std::pair<const char *, unsigned> FeatureCheckList[] = {
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{"64bit", RVV_REQ_RV64},
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{"xandesvdot", RVV_REQ_Xandesvdot},
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{"xandesvpackfph", RVV_REQ_Xandesvpackfph},
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{"xsfvcp", RVV_REQ_Xsfvcp},
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{"xsfvfnrclipxfqf", RVV_REQ_Xsfvfnrclipxfqf},

‎clang/lib/Support/RISCVVIntrinsicUtils.cpp

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Original file line numberDiff line numberDiff line change
@@ -1214,6 +1214,7 @@ llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, enum RVVRequire Require) {
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switch (Require) {
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STRINGIFY(RVV_REQ_RV64)
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STRINGIFY(RVV_REQ_Zvfhmin)
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STRINGIFY(RVV_REQ_Xandesvdot)
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STRINGIFY(RVV_REQ_Xandesvpackfph)
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STRINGIFY(RVV_REQ_Xsfvcp)
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STRINGIFY(RVV_REQ_Xsfvfnrclipxfqf)

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vd4dots.c

Lines changed: 170 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,170 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
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// RUN: -target-feature +xandesvdot -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <andes_vector.h>
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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//
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vint32mf2_t test_nds_vd4dots_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs1, vint8mf2_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32mf2(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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vint32m1_t test_nds_vd4dots_vv_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m1(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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vint32m2_t test_nds_vd4dots_vv_i32m2(vint32m2_t vd, vint8m2_t vs1, vint8m2_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m2(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_nds_vd4dots_vv_i32m4(vint32m4_t vd, vint8m4_t vs1, vint8m4_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m4(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
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//
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vint32m8_t test_nds_vd4dots_vv_i32m8(vint32m8_t vd, vint8m8_t vs1, vint8m8_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m8(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
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//
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vint64m1_t test_nds_vd4dots_vv_i64m1(vint64m1_t vd, vint16m1_t vs1, vint16m1_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i64m1(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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vint64m2_t test_nds_vd4dots_vv_i64m2(vint64m2_t vd, vint16m2_t vs1, vint16m2_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i64m2(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
77+
//
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vint64m4_t test_nds_vd4dots_vv_i64m4(vint64m4_t vd, vint16m4_t vs1, vint16m4_t vs2, size_t vl) {
79+
return __riscv_nds_vd4dots_vv_i64m4(vd, vs1, vs2, vl);
80+
}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.nds.vd4dots.nxv8i64.nxv32i16.nxv32i16.i64(<vscale x 8 x i64> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
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//
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vint64m8_t test_nds_vd4dots_vv_i64m8(vint64m8_t vd, vint16m8_t vs1, vint16m8_t vs2, size_t vl) {
88+
return __riscv_nds_vd4dots_vv_i64m8(vd, vs1, vs2, vl);
89+
}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32mf2_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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//
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vint32mf2_t test_nds_vd4dots_vv_i32mf2_m(vbool64_t mask, vint32mf2_t vd, vint8mf2_t vs1, vint8mf2_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32mf2_m(mask, vd, vs1, vs2, vl);
98+
}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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vint32m1_t test_nds_vd4dots_vv_i32m1_m(vbool32_t mask, vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
106+
return __riscv_nds_vd4dots_vv_i32m1_m(mask, vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m2_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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vint32m2_t test_nds_vd4dots_vv_i32m2_m(vbool16_t mask, vint32m2_t vd, vint8m2_t vs1, vint8m2_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m2_m(mask, vd, vs1, vs2, vl);
116+
}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m4_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_nds_vd4dots_vv_i32m4_m(vbool8_t mask, vint32m4_t vd, vint8m4_t vs1, vint8m4_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m4_m(mask, vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i32m8_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
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//
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vint32m8_t test_nds_vd4dots_vv_i32m8_m(vbool4_t mask, vint32m8_t vd, vint8m8_t vs1, vint8m8_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i32m8_m(mask, vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.mask.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
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//
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vint64m1_t test_nds_vd4dots_vv_i64m1_m(vbool64_t mask, vint64m1_t vd, vint16m1_t vs1, vint16m1_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i64m1_m(mask, vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m2_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.mask.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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vint64m2_t test_nds_vd4dots_vv_i64m2_m(vbool32_t mask, vint64m2_t vd, vint16m2_t vs1, vint16m2_t vs2, size_t vl) {
151+
return __riscv_nds_vd4dots_vv_i64m2_m(mask, vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m4_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.mask.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
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//
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vint64m4_t test_nds_vd4dots_vv_i64m4_m(vbool16_t mask, vint64m4_t vd, vint16m4_t vs1, vint16m4_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i64m4_m(mask, vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: @test_nds_vd4dots_vv_i64m8_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.nds.vd4dots.mask.nxv8i64.nxv32i16.nxv32i16.i64(<vscale x 8 x i64> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
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//
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vint64m8_t test_nds_vd4dots_vv_i64m8_m(vbool8_t mask, vint64m8_t vd, vint16m8_t vs1, vint16m8_t vs2, size_t vl) {
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return __riscv_nds_vd4dots_vv_i64m8_m(mask, vd, vs1, vs2, vl);
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}

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