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[MISched] Add templates for creating custom schedulers
We rename `createGenericSchedLive` and `createGenericSchedPostRA` to `createSchedLive` and `createSchedPostRA`, and add a template parameter `Strategy` which is the generic implementation by default. This can simplify some code for targets that have custom scheduler strategy.
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+58
-69
lines changed

9 files changed

+58
-69
lines changed

‎llvm/include/llvm/CodeGen/MachineScheduler.h

Lines changed: 36 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
//
4242
// ScheduleDAGInstrs *<Target>TargetMachine::
4343
// createMachineScheduler(MachineSchedContext *C) {
44-
// ScheduleDAGMI *DAG = createGenericSchedLive(C);
44+
// ScheduleDAGMI *DAG = createSchedLive(C);
4545
// DAG->addMutation(new CustomDAGMutation(...));
4646
// return DAG;
4747
// }
@@ -1383,14 +1383,6 @@ class LLVM_ABI PostGenericScheduler : public GenericSchedulerBase {
13831383
void pickNodeFromQueue(SchedBoundary &Zone, SchedCandidate &Cand);
13841384
};
13851385

1386-
/// Create the standard converging machine scheduler. This will be used as the
1387-
/// default scheduler if the target does not set a default.
1388-
/// Adds default DAG mutations.
1389-
LLVM_ABI ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C);
1390-
1391-
/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
1392-
LLVM_ABI ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C);
1393-
13941386
/// If ReorderWhileClustering is set to true, no attempt will be made to
13951387
/// reduce reordering due to store clustering.
13961388
LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
@@ -1409,6 +1401,41 @@ LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
14091401
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
14101402
const TargetRegisterInfo *TRI);
14111403

1404+
/// Create the standard converging machine scheduler. This will be used as the
1405+
/// default scheduler if the target does not set a default.
1406+
/// Adds default DAG mutations.
1407+
template <typename Strategy = GenericScheduler>
1408+
LLVM_ABI ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {
1409+
ScheduleDAGMILive *DAG =
1410+
new ScheduleDAGMILive(C, std::make_unique<Strategy>(C));
1411+
// Register DAG post-processors.
1412+
//
1413+
// FIXME: extend the mutation API to allow earlier mutations to instantiate
1414+
// data and pass it to later mutations. Have a single mutation that gathers
1415+
// the interesting nodes in one pass.
1416+
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
1417+
1418+
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
1419+
// Add MacroFusion mutation if fusions are not empty.
1420+
const auto &MacroFusions = STI.getMacroFusions();
1421+
if (!MacroFusions.empty())
1422+
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
1423+
return DAG;
1424+
}
1425+
1426+
/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
1427+
template <typename Strategy = PostGenericScheduler>
1428+
LLVM_ABI ScheduleDAGMI *createSchedPostRA(MachineSchedContext *C) {
1429+
ScheduleDAGMI *DAG = new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
1430+
/*RemoveKillFlags=*/true);
1431+
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
1432+
// Add MacroFusion mutation if fusions are not empty.
1433+
const auto &MacroFusions = STI.getMacroFusions();
1434+
if (!MacroFusions.empty())
1435+
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
1436+
return DAG;
1437+
}
1438+
14121439
class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
14131440
// FIXME: Remove this member once RegisterClassInfo is queryable as an
14141441
// analysis.

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 3 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -547,7 +547,7 @@ ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
547547
return Scheduler;
548548

549549
// Default to GenericScheduler.
550-
return createGenericSchedLive(this);
550+
return createSchedLive(this);
551551
}
552552

553553
bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
@@ -595,7 +595,7 @@ ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
595595
return Scheduler;
596596

597597
// Default to GenericScheduler.
598-
return createGenericSchedPostRA(this);
598+
return createSchedPostRA(this);
599599
}
600600

601601
bool PostMachineSchedulerImpl::run(MachineFunction &Func,
@@ -4273,28 +4273,8 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
42734273
}
42744274
}
42754275

4276-
/// Create the standard converging machine scheduler. This will be used as the
4277-
/// default scheduler if the target does not set a default.
4278-
ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
4279-
ScheduleDAGMILive *DAG =
4280-
new ScheduleDAGMILive(C, std::make_unique<GenericScheduler>(C));
4281-
// Register DAG post-processors.
4282-
//
4283-
// FIXME: extend the mutation API to allow earlier mutations to instantiate
4284-
// data and pass it to later mutations. Have a single mutation that gathers
4285-
// the interesting nodes in one pass.
4286-
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
4287-
4288-
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
4289-
// Add MacroFusion mutation if fusions are not empty.
4290-
const auto &MacroFusions = STI.getMacroFusions();
4291-
if (!MacroFusions.empty())
4292-
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
4293-
return DAG;
4294-
}
4295-
42964276
static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
4297-
return createGenericSchedLive(C);
4277+
return createSchedLive(C);
42984278
}
42994279

43004280
static MachineSchedRegistry
@@ -4598,18 +4578,6 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
45984578
}
45994579
}
46004580

4601-
ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
4602-
ScheduleDAGMI *DAG =
4603-
new ScheduleDAGMI(C, std::make_unique<PostGenericScheduler>(C),
4604-
/*RemoveKillFlags=*/true);
4605-
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
4606-
// Add MacroFusion mutation if fusions are not empty.
4607-
const auto &MacroFusions = STI.getMacroFusions();
4608-
if (!MacroFusions.empty())
4609-
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
4610-
return DAG;
4611-
}
4612-
46134581
//===----------------------------------------------------------------------===//
46144582
// ILP Scheduler. Currently for experimental analysis of heuristics.
46154583
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
487487
ScheduleDAGInstrs *
488488
AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
489489
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
490-
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
490+
ScheduleDAGMILive *DAG = createSchedLive(C);
491491
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
492492
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
493493
if (ST.hasFusion())
@@ -498,9 +498,7 @@ AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
498498
ScheduleDAGInstrs *
499499
AArch64TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
500500
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
501-
ScheduleDAGMI *DAG =
502-
new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
503-
/* RemoveKillFlags=*/true);
501+
ScheduleDAGMI *DAG = createSchedPostRA<AArch64PostRASchedStrategy>(C);
504502
if (ST.hasFusion()) {
505503
// Run the Macro Fusion after RA again since literals are expanded from
506504
// pseudos then (v. addPreSched2()).

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -751,7 +751,7 @@ StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
751751
llvm::ScheduleDAGInstrs *
752752
AMDGPUTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
753753
const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
754-
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
754+
ScheduleDAGMILive *DAG = createSchedLive(C);
755755
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
756756
if (ST.shouldClusterStores())
757757
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -328,7 +328,7 @@ ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
328328

329329
ScheduleDAGInstrs *
330330
ARMBaseTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
331-
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
331+
ScheduleDAGMILive *DAG = createSchedLive(C);
332332
// add DAG Mutations here.
333333
const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
334334
if (ST.hasFusion())
@@ -338,7 +338,7 @@ ARMBaseTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
338338

339339
ScheduleDAGInstrs *
340340
ARMBaseTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
341-
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
341+
ScheduleDAGMI *DAG = createSchedPostRA(C);
342342
// add DAG Mutations here.
343343
const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
344344
if (ST.hasFusion())

‎llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -310,12 +310,10 @@ getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
310310

311311
static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
312312
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
313-
ScheduleDAGMILive *DAG =
314-
new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
315-
std::make_unique<PPCPreRASchedStrategy>(C) :
316-
std::make_unique<GenericScheduler>(C));
313+
ScheduleDAGMILive *DAG = ST.usePPCPreRASchedStrategy()
314+
? createSchedLive<PPCPreRASchedStrategy>(C)
315+
: createSchedLive<GenericScheduler>(C);
317316
// add DAG Mutations here.
318-
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
319317
if (ST.hasStoreFusion())
320318
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
321319
if (ST.hasFusion())
@@ -324,13 +322,12 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
324322
return DAG;
325323
}
326324

327-
static ScheduleDAGInstrs *createPPCPostMachineScheduler(
328-
MachineSchedContext *C) {
325+
static ScheduleDAGInstrs *
326+
createPPCPostMachineScheduler(MachineSchedContext *C) {
329327
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
330-
ScheduleDAGMI *DAG =
331-
new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
332-
std::make_unique<PPCPostRASchedStrategy>(C) :
333-
std::make_unique<PostGenericScheduler>(C), true);
328+
ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
329+
? createSchedPostRA<PPCPostRASchedStrategy>(C)
330+
: createSchedPostRA<PostGenericScheduler>(C);
334331
// add DAG Mutations here.
335332
if (ST.hasStoreFusion())
336333
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ ScheduleDAGInstrs *
300300
RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
301301
ScheduleDAGMILive *DAG = nullptr;
302302
if (EnableMISchedLoadStoreClustering) {
303-
DAG = createGenericSchedLive(C);
303+
DAG = createSchedLive(C);
304304
DAG->addMutation(createLoadClusterDAGMutation(
305305
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
306306
DAG->addMutation(createStoreClusterDAGMutation(
@@ -309,7 +309,7 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
309309

310310
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
311311
if (!DisableVectorMaskMutation && ST.hasVInstructions()) {
312-
DAG = DAG ? DAG : createGenericSchedLive(C);
312+
DAG = DAG ? DAG : createSchedLive(C);
313313
DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
314314
}
315315
return DAG;
@@ -319,7 +319,7 @@ ScheduleDAGInstrs *
319319
RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
320320
ScheduleDAGMI *DAG = nullptr;
321321
if (EnablePostMISchedLoadStoreClustering) {
322-
DAG = createGenericSchedPostRA(C);
322+
DAG = createSchedPostRA(C);
323323
DAG->addMutation(createLoadClusterDAGMutation(
324324
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
325325
DAG->addMutation(createStoreClusterDAGMutation(

‎llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -209,8 +209,7 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
209209

210210
ScheduleDAGInstrs *
211211
SystemZTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
212-
return new ScheduleDAGMI(C, std::make_unique<SystemZPostRASchedStrategy>(C),
213-
/*RemoveKillFlags=*/true);
212+
return createSchedPostRA<SystemZPostRASchedStrategy>(C);
214213
}
215214

216215
namespace {

‎llvm/lib/Target/X86/X86TargetMachine.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -378,14 +378,14 @@ void X86TargetMachine::reset() { SubtargetMap.clear(); }
378378

379379
ScheduleDAGInstrs *
380380
X86TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
381-
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
381+
ScheduleDAGMILive *DAG = createSchedLive(C);
382382
DAG->addMutation(createX86MacroFusionDAGMutation());
383383
return DAG;
384384
}
385385

386386
ScheduleDAGInstrs *
387387
X86TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
388-
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
388+
ScheduleDAGMI *DAG = createSchedPostRA(C);
389389
DAG->addMutation(createX86MacroFusionDAGMutation());
390390
return DAG;
391391
}

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