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[RISCV] Add bltu/bgeu zero => bnez/beqz canonicalisation to RISCVInstrInfo::simplifyInstruction (#141775)
We can end up with bltu/bgeu with the zero register as the 0th operand after tail duplication and then machine copy propagation. Canonicalising in simplifyInstruction (called from MachineCopyPropagation) both produces easier to read assembly output, and means it's possible that the compressed c.beqz/c.bnez forms are produced.
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llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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@@ -4189,6 +4189,24 @@ bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
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return true;
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}
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break;
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case RISCV::BLTU:
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// bltu zero, rs, imm => bne rs, zero, imm
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if (MI.getOperand(0).getReg() == RISCV::X0) {
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MachineOperand MO0 = MI.getOperand(0);
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MI.removeOperand(0);
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MI.insert(MI.operands_begin() + 1, {MO0});
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MI.setDesc(get(RISCV::BNE));
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}
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break;
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case RISCV::BGEU:
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// bgeu zero, rs, imm => beq rs, zero, imm
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if (MI.getOperand(0).getReg() == RISCV::X0) {
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MachineOperand MO0 = MI.getOperand(0);
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MI.removeOperand(0);
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MI.insert(MI.operands_begin() + 1, {MO0});
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MI.setDesc(get(RISCV::BEQ));
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}
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break;
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}
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return false;
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}

llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir

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@@ -742,3 +742,39 @@ body: |
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renamable $x10 = MAXU renamable $x11, renamable $x11
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PseudoRET implicit $x10
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...
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---
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name: bltu
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body: |
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; CHECK-LABEL: name: bltu
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x11 = COPY $x12
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; CHECK-NEXT: BNE $x12, $x0, %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: PseudoRET
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bb.0:
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renamable $x11 = COPY $x12
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BLTU $x0, renamable $x11, %bb.1
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bb.1:
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PseudoRET
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...
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---
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name: bgeu
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body: |
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; CHECK-LABEL: name: bgeu
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x11 = COPY $x12
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; CHECK-NEXT: BEQ $x12, $x0, %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: PseudoRET
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bb.0:
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renamable $x11 = COPY $x12
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BGEU $x0, renamable $x11, %bb.1
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bb.1:
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PseudoRET
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...

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