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[MLIR][NVVM] Rename cvt Ops to convert
This patch renames the cvt Ops to `convert` in the NVVM dialect to be more descriptive.
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6 files changed

+75
-74
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6 files changed

+75
-74
lines changed

‎mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1033,7 +1033,7 @@ def SaturationModeAttr : EnumAttr<NVVM_Dialect, SaturationMode, "sat_mode"> {
10331033
let assemblyFormat = "`<` $value `>`";
10341034
}
10351035

1036-
def NVVM_CvtFloatToTF32Op : NVVM_Op<"cvt.float.to.tf32"> {
1036+
def NVVM_ConvertFloatToTF32Op : NVVM_Op<"convert.float.to.tf32"> {
10371037
let summary = "Convert the given float input to TF32";
10381038
let description = [{
10391039
This Op converts the given f32 input to tf32.
@@ -1062,7 +1062,7 @@ def NVVM_CvtFloatToTF32Op : NVVM_Op<"cvt.float.to.tf32"> {
10621062
}];
10631063

10641064
string llvmBuilder = [{
1065-
auto intId = NVVM::CvtFloatToTF32Op::getIntrinsicID($rnd, $sat, $relu);
1065+
auto intId = NVVM::ConvertFloatToTF32Op::getIntrinsicID($rnd, $sat, $relu);
10661066
$res = createIntrinsicCall(builder, intId, {$src});
10671067
}];
10681068
}
@@ -1079,7 +1079,7 @@ def CVTFP6TypeAttr : EnumAttr<NVVM_Dialect, CVTFP6Type, "cvt_fp6_type"> {
10791079
let assemblyFormat = "`<` $value `>`";
10801080
}
10811081

1082-
def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
1082+
def NVVM_ConvertF32x2ToF6x2Op : NVVM_Op<"convert.f32x2.to.f6x2"> {
10831083
let summary = "Convert a pair of float inputs to f6x2";
10841084
let description = [{
10851085
This Op converts each of the given float inputs to the specified fp6 type.
@@ -1111,7 +1111,7 @@ def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
11111111
}];
11121112

11131113
string llvmBuilder = [{
1114-
auto intId = NVVM::CvtF32x2ToF6x2Op::getIntrinsicID($type, $relu);
1114+
auto intId = NVVM::ConvertF32x2ToF6x2Op::getIntrinsicID($type, $relu);
11151115
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
11161116
if(op.getDst().getType().isInteger(16))
11171117
$dst = packedI16;
@@ -1134,7 +1134,7 @@ def CVTFP8TypeAttr : EnumAttr<NVVM_Dialect, CVTFP8Type, "cvt_fp8_type"> {
11341134
let assemblyFormat = "`<` $value `>`";
11351135
}
11361136

1137-
def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
1137+
def NVVM_ConvertF32x2ToF8x2Op : NVVM_Op<"convert.f32x2.to.f8x2"> {
11381138
let summary = "Convert a pair of float inputs to f8x2";
11391139
let description = [{
11401140
This Op converts each of the given float inputs to the specified fp8 type.
@@ -1171,7 +1171,7 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
11711171
}];
11721172

11731173
string llvmBuilder = [{
1174-
auto intId = NVVM::CvtF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
1174+
auto intId = NVVM::ConvertF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
11751175
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
11761176
if(op.getDst().getType().isInteger(16))
11771177
$dst = packedI16;
@@ -1181,7 +1181,7 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
11811181
}];
11821182
}
11831183

1184-
def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
1184+
def NVVM_ConvertF16x2ToF8x2Op : NVVM_Op<"convert.f16x2.to.f8x2"> {
11851185
let summary = "Convert an f16x2 input to f8x2";
11861186
let description = [{
11871187
This Op converts the given f16 inputs in an f16x2 vector to the specified
@@ -1214,7 +1214,7 @@ def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
12141214
}];
12151215

12161216
string llvmBuilder = [{
1217-
auto intId = NVVM::CvtF16x2ToF8x2Op::getIntrinsicID($type, $relu);
1217+
auto intId = NVVM::ConvertF16x2ToF8x2Op::getIntrinsicID($type, $relu);
12181218
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
12191219
if(op.getDst().getType().isInteger(16))
12201220
$dst = packedI16;
@@ -1224,7 +1224,7 @@ def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
12241224
}];
12251225
}
12261226

1227-
def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
1227+
def NVVM_ConvertBF16x2ToF8x2Op : NVVM_Op<"convert.bf16x2.to.f8x2"> {
12281228
let summary = "Convert a pair of bf16 inputs to f8x2";
12291229
let description = [{
12301230
This Op converts the given bf16 inputs in a bf16x2 vector to the specified
@@ -1258,7 +1258,7 @@ def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
12581258
}];
12591259

12601260
string llvmBuilder = [{
1261-
auto intId = NVVM::CvtBF16x2ToF8x2Op::getIntrinsicID($rnd, $sat);
1261+
auto intId = NVVM::ConvertBF16x2ToF8x2Op::getIntrinsicID($rnd, $sat);
12621262
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
12631263
if(op.getDst().getType().isInteger(16))
12641264
$dst = packedI16;

‎mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ LogicalResult CpAsyncBulkTensorReduceOp::verify() {
117117
getLoc());
118118
}
119119

120-
LogicalResult CvtFloatToTF32Op::verify() {
120+
LogicalResult ConvertFloatToTF32Op::verify() {
121121
using RndMode = NVVM::FPRoundingMode;
122122
switch (getRnd()) {
123123
case RndMode::RNA:
@@ -134,7 +134,7 @@ LogicalResult CvtFloatToTF32Op::verify() {
134134
return success();
135135
}
136136

137-
LogicalResult CvtF32x2ToF8x2Op::verify() {
137+
LogicalResult ConvertF32x2ToF8x2Op::verify() {
138138
using RndMode = NVVM::FPRoundingMode;
139139
using SatMode = NVVM::SaturationMode;
140140

@@ -166,15 +166,15 @@ LogicalResult CvtF32x2ToF8x2Op::verify() {
166166
return success();
167167
}
168168

169-
LogicalResult CvtF16x2ToF8x2Op::verify() {
169+
LogicalResult ConvertF16x2ToF8x2Op::verify() {
170170
if (getType() == CVTFP8Type::UE8M0)
171171
return emitOpError("Only .e4m3 or .e5m2 types are supported for "
172172
"conversions from f16x2 to f8x2.");
173173

174174
return success();
175175
}
176176

177-
LogicalResult CvtBF16x2ToF8x2Op::verify() {
177+
LogicalResult ConvertBF16x2ToF8x2Op::verify() {
178178
using RndMode = NVVM::FPRoundingMode;
179179

180180
if (getType() != CVTFP8Type::UE8M0)
@@ -1336,9 +1336,9 @@ llvm::Intrinsic::ID CpAsyncBulkTensorReduceOp::getIntrinsicID(
13361336
hasSatFinite ? CVT_F2TF32_ID_IMPL(rnd, relu, sf) \
13371337
: CVT_F2TF32_ID_IMPL(rnd, relu, )
13381338

1339-
llvm::Intrinsic::ID CvtFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1340-
NVVM::SaturationMode sat,
1341-
bool hasRelu) {
1339+
llvm::Intrinsic::ID
1340+
ConvertFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1341+
NVVM::SaturationMode sat, bool hasRelu) {
13421342
using RndMode = NVVM::FPRoundingMode;
13431343
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
13441344
switch (rnd) {
@@ -1357,14 +1357,15 @@ llvm::Intrinsic::ID CvtFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
13571357
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu_satfinite \
13581358
: llvm::Intrinsic::nvvm_ff_to_##type##_rn_satfinite
13591359

1360-
llvm::Intrinsic::ID CvtF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
1361-
bool hasRelu) {
1360+
llvm::Intrinsic::ID ConvertF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
1361+
bool hasRelu) {
13621362
switch (type) {
13631363
case NVVM::CVTFP6Type::E2M3:
13641364
return GET_F32x2_TO_F6x2_ID(e2m3x2, hasRelu);
13651365
case NVVM::CVTFP6Type::E3M2:
13661366
return GET_F32x2_TO_F6x2_ID(e3m2x2, hasRelu);
13671367
}
1368+
llvm_unreachable("Invalid conversion in ConvertF32x2ToF6x2Op");
13681369
}
13691370

13701371
#define GET_F32x2_TO_F8X2_US_ID(rnd, has_satf) \
@@ -1375,10 +1376,10 @@ llvm::Intrinsic::ID CvtF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
13751376
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu \
13761377
: llvm::Intrinsic::nvvm_ff_to_##type##_rn
13771378

1378-
llvm::Intrinsic::ID CvtF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1379-
NVVM::FPRoundingMode rnd,
1380-
NVVM::SaturationMode sat,
1381-
bool hasRelu) {
1379+
llvm::Intrinsic::ID
1380+
ConvertF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1381+
NVVM::FPRoundingMode rnd,
1382+
NVVM::SaturationMode sat, bool hasRelu) {
13821383
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
13831384
bool hasRoundingModeRZ = (rnd == NVVM::FPRoundingMode::RZ);
13841385
bool hasRoundingModeRP = (rnd == NVVM::FPRoundingMode::RP);
@@ -1401,8 +1402,8 @@ llvm::Intrinsic::ID CvtF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
14011402
has_relu ? llvm::Intrinsic::nvvm_f16x2_to_##type##_rn_relu \
14021403
: llvm::Intrinsic::nvvm_f16x2_to_##type##_rn
14031404

1404-
llvm::Intrinsic::ID CvtF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1405-
bool hasRelu) {
1405+
llvm::Intrinsic::ID ConvertF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1406+
bool hasRelu) {
14061407
switch (type) {
14071408
case NVVM::CVTFP8Type::E4M3:
14081409
return GET_F16x2_TO_F8X2_ID(e4m3x2, hasRelu);
@@ -1418,8 +1419,8 @@ llvm::Intrinsic::ID CvtF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
14181419
: llvm::Intrinsic::nvvm_bf16x2_to_ue8m0x2_##rnd
14191420

14201421
llvm::Intrinsic::ID
1421-
CvtBF16x2ToF8x2Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1422-
NVVM::SaturationMode sat) {
1422+
ConvertBF16x2ToF8x2Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1423+
NVVM::SaturationMode sat) {
14231424
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
14241425
switch (rnd) {
14251426
case NVVM::FPRoundingMode::RZ:

‎mlir/test/Target/LLVMIR/nvvm/cvt_fp6x2.mlir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,19 @@
33
// CHECK-LABEL: @convert_f32x2_to_fp6x2_packed
44
llvm.func @convert_f32x2_to_fp6x2_packed(%srcA : f32, %srcB : f32) {
55
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
6-
%res1 = nvvm.cvt.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
6+
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
77
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
8-
%res2 = nvvm.cvt.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
8+
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
99
llvm.return
1010
}
1111

1212
// CHECK-LABEL: @convert_f32x2_to_fp6x2_vector
1313
llvm.func @convert_f32x2_to_fp6x2_vector(%srcA : f32, %srcB : f32) {
1414
//CHECK: %[[res0:.*]] = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
1515
//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res0]] to <2 x i8>
16-
%res1 = nvvm.cvt.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
16+
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
1717
//CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
1818
//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
19-
%res2 = nvvm.cvt.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
19+
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
2020
llvm.return
2121
}

‎mlir/test/Target/LLVMIR/nvvm/cvt_fp8x2.mlir

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -5,42 +5,42 @@
55
// CHECK-LABEL: @convert_f32x2_to_f8x2_e4m3
66
llvm.func @convert_f32x2_to_f8x2_e4m3(%srcA : f32, %srcB : f32) {
77
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e4m3x2.rn(float %{{.*}}, float %{{.*}})
8-
%res1 = nvvm.cvt.f32x2.to.f8x2 <e4m3> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
8+
%res1 = nvvm.convert.f32x2.to.f8x2 <e4m3> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
99
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e4m3x2.rn.relu(float %{{.*}}, float %{{.*}})
10-
%res2 = nvvm.cvt.f32x2.to.f8x2 <e4m3> %srcA, %srcB {relu = true, rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
10+
%res2 = nvvm.convert.f32x2.to.f8x2 <e4m3> %srcA, %srcB {relu = true, rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
1111
llvm.return
1212
}
1313

1414
// CHECK-LABEL: @convert_f32x2_to_f8x2_e5m2
1515
llvm.func @convert_f32x2_to_f8x2_e5m2(%srcA : f32, %srcB : f32) {
1616
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e5m2x2.rn(float %{{.*}}, float %{{.*}})
17-
%res1 = nvvm.cvt.f32x2.to.f8x2 <e5m2> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
17+
%res1 = nvvm.convert.f32x2.to.f8x2 <e5m2> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
1818
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e5m2x2.rn.relu(float %{{.*}}, float %{{.*}})
19-
%res2 = nvvm.cvt.f32x2.to.f8x2 <e5m2> %srcA, %srcB {relu = true, rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
19+
%res2 = nvvm.convert.f32x2.to.f8x2 <e5m2> %srcA, %srcB {relu = true, rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : i16
2020
llvm.return
2121
}
2222

2323
// CHECK-LABEL: @convert_f32x2_to_f8x2_ue8m0
2424
llvm.func @convert_f32x2_to_f8x2_ue8m0(%srcA : f32, %srcB : f32) {
2525
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.ue8m0x2.rz(float %{{.*}}, float %{{.*}})
26-
%res1 = nvvm.cvt.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rz>} : i16
26+
%res1 = nvvm.convert.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rz>} : i16
2727
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.ue8m0x2.rp(float %{{.*}}, float %{{.*}})
28-
%res2 = nvvm.cvt.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rp>} : i16
28+
%res2 = nvvm.convert.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rp>} : i16
2929
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.ue8m0x2.rz.satfinite(float %{{.*}}, float %{{.*}})
30-
%res3 = nvvm.cvt.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rz>, sat = #nvvm.sat_mode<satfinite>} : i16
30+
%res3 = nvvm.convert.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rz>, sat = #nvvm.sat_mode<satfinite>} : i16
3131
// CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.ue8m0x2.rp.satfinite(float %{{.*}}, float %{{.*}})
32-
%res4 = nvvm.cvt.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<satfinite>} : i16
32+
%res4 = nvvm.convert.f32x2.to.f8x2 <ue8m0> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<satfinite>} : i16
3333
llvm.return
3434
}
3535

3636
// CHECK-LABEL: @convert_f32x2_to_f8x2_vector_return
3737
llvm.func @convert_f32x2_to_f8x2_vector_return(%srcA : f32, %srcB : f32) {
3838
// CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.ff.to.e4m3x2.rn(float %{{.*}}, float %{{.*}})
3939
// CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
40-
%res1 = nvvm.cvt.f32x2.to.f8x2 <e4m3> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : vector<2xi8>
40+
%res1 = nvvm.convert.f32x2.to.f8x2 <e4m3> %srcA, %srcB {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : vector<2xi8>
4141
// CHECK: %[[res2:.*]] = call i16 @llvm.nvvm.ff.to.e4m3x2.rn.relu(float %{{.*}}, float %{{.*}})
4242
// CHECK-NEXT: %{{.*}} = bitcast i16 %[[res2]] to <2 x i8>
43-
%res2 = nvvm.cvt.f32x2.to.f8x2 <e4m3> %srcA, %srcB {relu = true, rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : vector<2xi8>
43+
%res2 = nvvm.convert.f32x2.to.f8x2 <e4m3> %srcA, %srcB {relu = true, rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<satfinite>} : vector<2xi8>
4444
llvm.return
4545
}
4646

@@ -49,29 +49,29 @@ llvm.func @convert_f32x2_to_f8x2_vector_return(%srcA : f32, %srcB : f32) {
4949
// CHECK-LABEL: @convert_f16x2_to_f8x2_e4m3
5050
llvm.func @convert_f16x2_to_f8x2_e4m3(%src : vector<2xf16>) {
5151
// CHECK: %{{.*}} = call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn(<2 x half> %{{.*}})
52-
%res1 = nvvm.cvt.f16x2.to.f8x2 <e4m3> %src : vector<2xf16> -> i16
52+
%res1 = nvvm.convert.f16x2.to.f8x2 <e4m3> %src : vector<2xf16> -> i16
5353
// CHECK: %{{.*}} = call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn.relu(<2 x half> %{{.*}})
54-
%res2 = nvvm.cvt.f16x2.to.f8x2 <e4m3> %src {relu = true} : vector<2xf16> -> i16
54+
%res2 = nvvm.convert.f16x2.to.f8x2 <e4m3> %src {relu = true} : vector<2xf16> -> i16
5555
llvm.return
5656
}
5757

5858
// CHECK-LABEL: @convert_f16x2_to_f8x2_e5m2
5959
llvm.func @convert_f16x2_to_f8x2_e5m2(%src : vector<2xf16>) {
6060
// CHECK: %{{.*}} = call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn(<2 x half> %{{.*}})
61-
%res1 = nvvm.cvt.f16x2.to.f8x2 <e5m2> %src : vector<2xf16> -> i16
61+
%res1 = nvvm.convert.f16x2.to.f8x2 <e5m2> %src : vector<2xf16> -> i16
6262
// CHECK: %{{.*}} = call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn.relu(<2 x half> %{{.*}})
63-
%res2 = nvvm.cvt.f16x2.to.f8x2 <e5m2> %src {relu = true} : vector<2xf16> -> i16
63+
%res2 = nvvm.convert.f16x2.to.f8x2 <e5m2> %src {relu = true} : vector<2xf16> -> i16
6464
llvm.return
6565
}
6666

6767
// CHECK-LABEL: @convert_f16x2_to_f8x2_vector_return
6868
llvm.func @convert_f16x2_to_f8x2_vector_return(%src : vector<2xf16>) {
6969
// CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn(<2 x half> %{{.*}})
7070
// CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
71-
%res1 = nvvm.cvt.f16x2.to.f8x2 <e4m3> %src : vector<2xf16> -> vector<2xi8>
71+
%res1 = nvvm.convert.f16x2.to.f8x2 <e4m3> %src : vector<2xf16> -> vector<2xi8>
7272
// CHECK: %[[res2:.*]] = call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn(<2 x half> %{{.*}})
7373
// CHECK-NEXT: %{{.*}} = bitcast i16 %[[res2]] to <2 x i8>
74-
%res2 = nvvm.cvt.f16x2.to.f8x2 <e5m2> %src : vector<2xf16> -> vector<2xi8>
74+
%res2 = nvvm.convert.f16x2.to.f8x2 <e5m2> %src : vector<2xf16> -> vector<2xi8>
7575
llvm.return
7676
}
7777

@@ -80,23 +80,23 @@ llvm.func @convert_f16x2_to_f8x2_vector_return(%src : vector<2xf16>) {
8080
// CHECK-LABEL: @convert_bf16x2_to_f8x2_ue8m0
8181
llvm.func @convert_bf16x2_to_f8x2_ue8m0(%src : vector<2xbf16>) {
8282
// CHECK: %{{.*}} = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> %{{.*}})
83-
%res1 = nvvm.cvt.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rz>} : vector<2xbf16> -> i16
83+
%res1 = nvvm.convert.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rz>} : vector<2xbf16> -> i16
8484
// CHECK: %{{.*}} = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> %{{.*}})
85-
%res2 = nvvm.cvt.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rp>} : vector<2xbf16> -> i16
85+
%res2 = nvvm.convert.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rp>} : vector<2xbf16> -> i16
8686
// CHECK: %{{.*}} = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> %{{.*}})
87-
%res3 = nvvm.cvt.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rz>, sat = #nvvm.sat_mode<satfinite>} : vector<2xbf16> -> i16
87+
%res3 = nvvm.convert.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rz>, sat = #nvvm.sat_mode<satfinite>} : vector<2xbf16> -> i16
8888
// CHECK: %{{.*}} = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> %{{.*}})
89-
%res4 = nvvm.cvt.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<satfinite>} : vector<2xbf16> -> i16
89+
%res4 = nvvm.convert.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<satfinite>} : vector<2xbf16> -> i16
9090
llvm.return
9191
}
9292

9393
// CHECK-LABEL: @convert_bf16x2_to_f8x2_vector_return
9494
llvm.func @convert_bf16x2_to_f8x2_vector_return(%src : vector<2xbf16>) {
9595
// CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> %{{.*}})
9696
// CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
97-
%res1 = nvvm.cvt.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rz>} : vector<2xbf16> -> vector<2xi8>
97+
%res1 = nvvm.convert.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rz>} : vector<2xbf16> -> vector<2xi8>
9898
// CHECK: %[[res2:.*]] = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> %{{.*}})
9999
// CHECK-NEXT: %{{.*}} = bitcast i16 %[[res2]] to <2 x i8>
100-
%res2 = nvvm.cvt.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<satfinite>} : vector<2xbf16> -> vector<2xi8>
100+
%res2 = nvvm.convert.bf16x2.to.f8x2 <ue8m0> %src {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<satfinite>} : vector<2xbf16> -> vector<2xi8>
101101
llvm.return
102102
}

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