Skip to content

Commit 8abe862

Browse files
Wolfram70Wolfram70
committed
[MLIR][NVVM] Rename cvt Ops to convert
This patch renames the cvt Ops and related structures to `convert` in the NVVM dialect to be more descriptive.
1 parent 690a30f commit 8abe862

File tree

6 files changed

+106
-105
lines changed

6 files changed

+106
-105
lines changed

‎mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1033,7 +1033,7 @@ def SaturationModeAttr : EnumAttr<NVVM_Dialect, SaturationMode, "sat_mode"> {
10331033
let assemblyFormat = "`<` $value `>`";
10341034
}
10351035

1036-
def NVVM_CvtFloatToTF32Op : NVVM_Op<"cvt.float.to.tf32"> {
1036+
def NVVM_ConvertFloatToTF32Op : NVVM_Op<"convert.float.to.tf32"> {
10371037
let summary = "Convert the given float input to TF32";
10381038
let description = [{
10391039
This Op converts the given f32 input to tf32.
@@ -1062,24 +1062,24 @@ def NVVM_CvtFloatToTF32Op : NVVM_Op<"cvt.float.to.tf32"> {
10621062
}];
10631063

10641064
string llvmBuilder = [{
1065-
auto intId = NVVM::CvtFloatToTF32Op::getIntrinsicID($rnd, $sat, $relu);
1065+
auto intId = NVVM::ConvertFloatToTF32Op::getIntrinsicID($rnd, $sat, $relu);
10661066
$res = createIntrinsicCall(builder, intId, {$src});
10671067
}];
10681068
}
10691069

1070-
def CVTFP6E2M3 : I32EnumAttrCase<"E2M3", 0, "e2m3">;
1071-
def CVTFP6E3M2 : I32EnumAttrCase<"E3M2", 1, "e3m2">;
1070+
def ConvertFP6E2M3 : I32EnumAttrCase<"E2M3", 0, "e2m3">;
1071+
def ConvertFP6E3M2 : I32EnumAttrCase<"E3M2", 1, "e3m2">;
10721072

1073-
def CVTFP6Type : I32EnumAttr<"CVTFP6Type", "NVVM CVTFP6Type kind",
1074-
[CVTFP6E2M3, CVTFP6E3M2]> {
1073+
def ConvertFP6Type : I32EnumAttr<"ConvertFP6Type", "NVVM ConvertFP6Type kind",
1074+
[ConvertFP6E2M3, ConvertFP6E3M2]> {
10751075
let genSpecializedAttr = 0;
10761076
let cppNamespace = "::mlir::NVVM";
10771077
}
1078-
def CVTFP6TypeAttr : EnumAttr<NVVM_Dialect, CVTFP6Type, "cvt_fp6_type"> {
1078+
def ConvertFP6TypeAttr : EnumAttr<NVVM_Dialect, ConvertFP6Type, "cvt_fp6_type"> {
10791079
let assemblyFormat = "`<` $value `>`";
10801080
}
10811081

1082-
def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
1082+
def NVVM_ConvertF32x2ToF6x2Op : NVVM_Op<"convert.f32x2.to.f6x2"> {
10831083
let summary = "Convert a pair of float inputs to f6x2";
10841084
let description = [{
10851085
This Op converts each of the given float inputs to the specified fp6 type.
@@ -1099,19 +1099,19 @@ def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
10991099

11001100
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
11011101
let arguments = (ins
1102-
CVTFP6TypeAttr:$type,
1102+
ConvertFP6TypeAttr:$type,
11031103
F32:$a,
11041104
F32:$b,
11051105
DefaultValuedAttr<BoolAttr, "false">:$relu);
11061106
let assemblyFormat = "$type $a `,` $b attr-dict `:` type($dst)";
11071107

11081108
let extraClassDeclaration = [{
1109-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::CVTFP6Type,
1109+
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP6Type,
11101110
bool hasRelu);
11111111
}];
11121112

11131113
string llvmBuilder = [{
1114-
auto intId = NVVM::CvtF32x2ToF6x2Op::getIntrinsicID($type, $relu);
1114+
auto intId = NVVM::ConvertF32x2ToF6x2Op::getIntrinsicID($type, $relu);
11151115
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
11161116
if(op.getDst().getType().isInteger(16))
11171117
$dst = packedI16;
@@ -1121,20 +1121,20 @@ def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
11211121
}];
11221122
}
11231123

1124-
def CVTFP8E4M3 : I32EnumAttrCase<"E4M3", 0, "e4m3">;
1125-
def CVTFP8E5M2 : I32EnumAttrCase<"E5M2", 1, "e5m2">;
1126-
def CVTFP8UE8M0 : I32EnumAttrCase<"UE8M0", 2, "ue8m0">;
1124+
def ConvertFP8E4M3 : I32EnumAttrCase<"E4M3", 0, "e4m3">;
1125+
def ConvertFP8E5M2 : I32EnumAttrCase<"E5M2", 1, "e5m2">;
1126+
def ConvertFP8UE8M0 : I32EnumAttrCase<"UE8M0", 2, "ue8m0">;
11271127

1128-
def CVTFP8Type : I32EnumAttr<"CVTFP8Type", "NVVM CVTFP8Type kind",
1129-
[CVTFP8E4M3, CVTFP8E5M2, CVTFP8UE8M0]> {
1128+
def ConvertFP8Type : I32EnumAttr<"ConvertFP8Type", "NVVM ConvertFP8Type kind",
1129+
[ConvertFP8E4M3, ConvertFP8E5M2, ConvertFP8UE8M0]> {
11301130
let genSpecializedAttr = 0;
11311131
let cppNamespace = "::mlir::NVVM";
11321132
}
1133-
def CVTFP8TypeAttr : EnumAttr<NVVM_Dialect, CVTFP8Type, "cvt_fp8_type"> {
1133+
def ConvertFP8TypeAttr : EnumAttr<NVVM_Dialect, ConvertFP8Type, "cvt_fp8_type"> {
11341134
let assemblyFormat = "`<` $value `>`";
11351135
}
11361136

1137-
def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
1137+
def NVVM_ConvertF32x2ToF8x2Op : NVVM_Op<"convert.f32x2.to.f8x2"> {
11381138
let summary = "Convert a pair of float inputs to f8x2";
11391139
let description = [{
11401140
This Op converts each of the given float inputs to the specified fp8 type.
@@ -1155,7 +1155,7 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
11551155
let hasVerifier = 1;
11561156
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
11571157
let arguments = (ins
1158-
CVTFP8TypeAttr:$type,
1158+
ConvertFP8TypeAttr:$type,
11591159
F32:$a,
11601160
F32:$b,
11611161
DefaultValuedAttr<FPRoundingModeAttr, "FPRoundingMode::NONE">:$rnd,
@@ -1164,14 +1164,14 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
11641164
let assemblyFormat = "$type $a `,` $b attr-dict `:` type($dst)";
11651165

11661166
let extraClassDeclaration = [{
1167-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::CVTFP8Type to,
1167+
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP8Type to,
11681168
NVVM::FPRoundingMode rnd,
11691169
NVVM::SaturationMode sat,
11701170
bool hasRelu);
11711171
}];
11721172

11731173
string llvmBuilder = [{
1174-
auto intId = NVVM::CvtF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
1174+
auto intId = NVVM::ConvertF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
11751175
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
11761176
if(op.getDst().getType().isInteger(16))
11771177
$dst = packedI16;
@@ -1181,7 +1181,7 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
11811181
}];
11821182
}
11831183

1184-
def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
1184+
def NVVM_ConvertF16x2ToF8x2Op : NVVM_Op<"convert.f16x2.to.f8x2"> {
11851185
let summary = "Convert an f16x2 input to f8x2";
11861186
let description = [{
11871187
This Op converts the given f16 inputs in an f16x2 vector to the specified
@@ -1203,18 +1203,18 @@ def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
12031203
let hasVerifier = 1;
12041204
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
12051205
let arguments = (ins
1206-
CVTFP8TypeAttr:$type,
1206+
ConvertFP8TypeAttr:$type,
12071207
VectorOfLengthAndType<[2], [F16]>:$a,
12081208
DefaultValuedAttr<BoolAttr, "false">:$relu);
12091209
let assemblyFormat = "$type $a attr-dict `:` type($a) `->` type($dst)";
12101210

12111211
let extraClassDeclaration = [{
1212-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::CVTFP8Type to,
1212+
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP8Type to,
12131213
bool hasRelu);
12141214
}];
12151215

12161216
string llvmBuilder = [{
1217-
auto intId = NVVM::CvtF16x2ToF8x2Op::getIntrinsicID($type, $relu);
1217+
auto intId = NVVM::ConvertF16x2ToF8x2Op::getIntrinsicID($type, $relu);
12181218
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
12191219
if(op.getDst().getType().isInteger(16))
12201220
$dst = packedI16;
@@ -1224,7 +1224,7 @@ def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
12241224
}];
12251225
}
12261226

1227-
def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
1227+
def NVVM_ConvertBF16x2ToF8x2Op : NVVM_Op<"convert.bf16x2.to.f8x2"> {
12281228
let summary = "Convert a pair of bf16 inputs to f8x2";
12291229
let description = [{
12301230
This Op converts the given bf16 inputs in a bf16x2 vector to the specified
@@ -1246,7 +1246,7 @@ def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
12461246
let hasVerifier = 1;
12471247
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
12481248
let arguments = (ins
1249-
CVTFP8TypeAttr:$type,
1249+
ConvertFP8TypeAttr:$type,
12501250
VectorOfLengthAndType<[2], [BF16]>:$a,
12511251
DefaultValuedAttr<FPRoundingModeAttr, "FPRoundingMode::NONE">:$rnd,
12521252
DefaultValuedAttr<SaturationModeAttr, "SaturationMode::NONE">:$sat);
@@ -1258,7 +1258,7 @@ def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
12581258
}];
12591259

12601260
string llvmBuilder = [{
1261-
auto intId = NVVM::CvtBF16x2ToF8x2Op::getIntrinsicID($rnd, $sat);
1261+
auto intId = NVVM::ConvertBF16x2ToF8x2Op::getIntrinsicID($rnd, $sat);
12621262
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
12631263
if(op.getDst().getType().isInteger(16))
12641264
$dst = packedI16;

‎mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp

Lines changed: 31 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ LogicalResult CpAsyncBulkTensorReduceOp::verify() {
117117
getLoc());
118118
}
119119

120-
LogicalResult CvtFloatToTF32Op::verify() {
120+
LogicalResult ConvertFloatToTF32Op::verify() {
121121
using RndMode = NVVM::FPRoundingMode;
122122
switch (getRnd()) {
123123
case RndMode::RNA:
@@ -134,7 +134,7 @@ LogicalResult CvtFloatToTF32Op::verify() {
134134
return success();
135135
}
136136

137-
LogicalResult CvtF32x2ToF8x2Op::verify() {
137+
LogicalResult ConvertF32x2ToF8x2Op::verify() {
138138
using RndMode = NVVM::FPRoundingMode;
139139
using SatMode = NVVM::SaturationMode;
140140

@@ -146,16 +146,16 @@ LogicalResult CvtF32x2ToF8x2Op::verify() {
146146
bool hasRelu = getRelu();
147147

148148
switch (getType()) {
149-
case CVTFP8Type::E4M3:
150-
case CVTFP8Type::E5M2:
149+
case ConvertFP8Type::E4M3:
150+
case ConvertFP8Type::E5M2:
151151
if (!isRoundingModeRN)
152152
return emitOpError("Only RN rounding mode is supported for conversions "
153153
"from f32x2 to .e4m3x2 or .e5m2x2 types");
154154
if (!isSatFinite)
155155
return emitOpError("Only SATFINITE saturation mode is supported for "
156156
"conversions from f32x2 to .e4m3x2 or .e5m2x2 types");
157157
break;
158-
case CVTFP8Type::UE8M0:
158+
case ConvertFP8Type::UE8M0:
159159
if (!(isRoundingModeRZ || isRoundingModeRP))
160160
return emitOpError("Only RZ or RP rounding modes are supported for "
161161
"conversions from f32x2 to .ue8m0x2 type");
@@ -166,18 +166,18 @@ LogicalResult CvtF32x2ToF8x2Op::verify() {
166166
return success();
167167
}
168168

169-
LogicalResult CvtF16x2ToF8x2Op::verify() {
170-
if (getType() == CVTFP8Type::UE8M0)
169+
LogicalResult ConvertF16x2ToF8x2Op::verify() {
170+
if (getType() == ConvertFP8Type::UE8M0)
171171
return emitOpError("Only .e4m3 or .e5m2 types are supported for "
172172
"conversions from f16x2 to f8x2.");
173173

174174
return success();
175175
}
176176

177-
LogicalResult CvtBF16x2ToF8x2Op::verify() {
177+
LogicalResult ConvertBF16x2ToF8x2Op::verify() {
178178
using RndMode = NVVM::FPRoundingMode;
179179

180-
if (getType() != CVTFP8Type::UE8M0)
180+
if (getType() != ConvertFP8Type::UE8M0)
181181
return emitOpError(
182182
"Only .ue8m0 type is supported for conversions from bf16x2 to f8x2.");
183183

@@ -1336,9 +1336,9 @@ llvm::Intrinsic::ID CpAsyncBulkTensorReduceOp::getIntrinsicID(
13361336
hasSatFinite ? CVT_F2TF32_ID_IMPL(rnd, relu, sf) \
13371337
: CVT_F2TF32_ID_IMPL(rnd, relu, )
13381338

1339-
llvm::Intrinsic::ID CvtFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1340-
NVVM::SaturationMode sat,
1341-
bool hasRelu) {
1339+
llvm::Intrinsic::ID
1340+
ConvertFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1341+
NVVM::SaturationMode sat, bool hasRelu) {
13421342
using RndMode = NVVM::FPRoundingMode;
13431343
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
13441344
switch (rnd) {
@@ -1357,14 +1357,15 @@ llvm::Intrinsic::ID CvtFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
13571357
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu_satfinite \
13581358
: llvm::Intrinsic::nvvm_ff_to_##type##_rn_satfinite
13591359

1360-
llvm::Intrinsic::ID CvtF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
1361-
bool hasRelu) {
1360+
llvm::Intrinsic::ID
1361+
ConvertF32x2ToF6x2Op::getIntrinsicID(NVVM::ConvertFP6Type type, bool hasRelu) {
13621362
switch (type) {
1363-
case NVVM::CVTFP6Type::E2M3:
1363+
case NVVM::ConvertFP6Type::E2M3:
13641364
return GET_F32x2_TO_F6x2_ID(e2m3x2, hasRelu);
1365-
case NVVM::CVTFP6Type::E3M2:
1365+
case NVVM::ConvertFP6Type::E3M2:
13661366
return GET_F32x2_TO_F6x2_ID(e3m2x2, hasRelu);
13671367
}
1368+
llvm_unreachable("Invalid conversion in ConvertF32x2ToF6x2Op");
13681369
}
13691370

13701371
#define GET_F32x2_TO_F8X2_US_ID(rnd, has_satf) \
@@ -1375,20 +1376,20 @@ llvm::Intrinsic::ID CvtF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
13751376
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu \
13761377
: llvm::Intrinsic::nvvm_ff_to_##type##_rn
13771378

1378-
llvm::Intrinsic::ID CvtF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1379-
NVVM::FPRoundingMode rnd,
1380-
NVVM::SaturationMode sat,
1381-
bool hasRelu) {
1379+
llvm::Intrinsic::ID
1380+
ConvertF32x2ToF8x2Op::getIntrinsicID(NVVM::ConvertFP8Type type,
1381+
NVVM::FPRoundingMode rnd,
1382+
NVVM::SaturationMode sat, bool hasRelu) {
13821383
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
13831384
bool hasRoundingModeRZ = (rnd == NVVM::FPRoundingMode::RZ);
13841385
bool hasRoundingModeRP = (rnd == NVVM::FPRoundingMode::RP);
13851386

13861387
switch (type) {
1387-
case NVVM::CVTFP8Type::E4M3:
1388+
case NVVM::ConvertFP8Type::E4M3:
13881389
return GET_F32x2_TO_F8X2_S_ID(e4m3x2, hasRelu);
1389-
case NVVM::CVTFP8Type::E5M2:
1390+
case NVVM::ConvertFP8Type::E5M2:
13901391
return GET_F32x2_TO_F8X2_S_ID(e5m2x2, hasRelu);
1391-
case NVVM::CVTFP8Type::UE8M0:
1392+
case NVVM::ConvertFP8Type::UE8M0:
13921393
if (hasRoundingModeRZ)
13931394
return GET_F32x2_TO_F8X2_US_ID(rz, hasSatFinite);
13941395
else if (hasRoundingModeRP)
@@ -1401,15 +1402,15 @@ llvm::Intrinsic::ID CvtF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
14011402
has_relu ? llvm::Intrinsic::nvvm_f16x2_to_##type##_rn_relu \
14021403
: llvm::Intrinsic::nvvm_f16x2_to_##type##_rn
14031404

1404-
llvm::Intrinsic::ID CvtF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1405-
bool hasRelu) {
1405+
llvm::Intrinsic::ID
1406+
ConvertF16x2ToF8x2Op::getIntrinsicID(NVVM::ConvertFP8Type type, bool hasRelu) {
14061407
switch (type) {
1407-
case NVVM::CVTFP8Type::E4M3:
1408+
case NVVM::ConvertFP8Type::E4M3:
14081409
return GET_F16x2_TO_F8X2_ID(e4m3x2, hasRelu);
1409-
case NVVM::CVTFP8Type::E5M2:
1410+
case NVVM::ConvertFP8Type::E5M2:
14101411
return GET_F16x2_TO_F8X2_ID(e5m2x2, hasRelu);
14111412
default:
1412-
llvm_unreachable("Invalid CVTFP8Type for CvtF16x2ToF8x2Op");
1413+
llvm_unreachable("Invalid ConvertFP8Type for CvtF16x2ToF8x2Op");
14131414
}
14141415
}
14151416

@@ -1418,8 +1419,8 @@ llvm::Intrinsic::ID CvtF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
14181419
: llvm::Intrinsic::nvvm_bf16x2_to_ue8m0x2_##rnd
14191420

14201421
llvm::Intrinsic::ID
1421-
CvtBF16x2ToF8x2Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1422-
NVVM::SaturationMode sat) {
1422+
ConvertBF16x2ToF8x2Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1423+
NVVM::SaturationMode sat) {
14231424
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
14241425
switch (rnd) {
14251426
case NVVM::FPRoundingMode::RZ:

‎mlir/test/Target/LLVMIR/nvvm/cvt_fp6x2.mlir renamed to ‎mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,19 @@
33
// CHECK-LABEL: @convert_f32x2_to_fp6x2_packed
44
llvm.func @convert_f32x2_to_fp6x2_packed(%srcA : f32, %srcB : f32) {
55
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
6-
%res1 = nvvm.cvt.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
6+
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
77
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
8-
%res2 = nvvm.cvt.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
8+
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
99
llvm.return
1010
}
1111

1212
// CHECK-LABEL: @convert_f32x2_to_fp6x2_vector
1313
llvm.func @convert_f32x2_to_fp6x2_vector(%srcA : f32, %srcB : f32) {
1414
//CHECK: %[[res0:.*]] = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
1515
//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res0]] to <2 x i8>
16-
%res1 = nvvm.cvt.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
16+
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
1717
//CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
1818
//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
19-
%res2 = nvvm.cvt.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
19+
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
2020
llvm.return
2121
}

0 commit comments

Comments
 (0)