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Merge branch 'main' into llvmdll-lib-IR
2 parents 7f3ea16 + 9ffbc8a commit aeabe8a

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‎.github/workflows/pr-code-format.yml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ jobs:
5555
- name: Install clang-format
5656
uses: aminya/setup-cpp@17c11551771948abc5752bbf3183482567c7caf0 # v1.1.1
5757
with:
58-
clangformat: 19.1.6
58+
clangformat: 20.1.5
5959

6060
- name: Setup Python env
6161
uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.4.0

‎clang/include/clang/Basic/SanitizerSpecialCaseList.h

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "llvm/ADT/StringRef.h"
2020
#include "llvm/Support/SpecialCaseList.h"
2121
#include <memory>
22+
#include <utility>
2223
#include <vector>
2324

2425
namespace llvm {
@@ -44,20 +45,24 @@ class SanitizerSpecialCaseList : public llvm::SpecialCaseList {
4445
StringRef Category = StringRef()) const;
4546

4647
// Query ignorelisted entries if any bit in Mask matches the entry's section.
47-
// Return 0 if not found. If found, return the line number (starts with 1).
48-
unsigned inSectionBlame(SanitizerMask Mask, StringRef Prefix, StringRef Query,
49-
StringRef Category = StringRef()) const;
48+
// Return NotFound (0,0) if not found. If found, return the file index number
49+
// and the line number (FileIdx, LineNo) (FileIdx starts with 1 and LineNo
50+
// starts with 0).
51+
std::pair<unsigned, unsigned>
52+
inSectionBlame(SanitizerMask Mask, StringRef Prefix, StringRef Query,
53+
StringRef Category = StringRef()) const;
5054

5155
protected:
5256
// Initialize SanitizerSections.
5357
void createSanitizerSections();
5458

5559
struct SanitizerSection {
56-
SanitizerSection(SanitizerMask SM, SectionEntries &E)
57-
: Mask(SM), Entries(E) {};
60+
SanitizerSection(SanitizerMask SM, SectionEntries &E, unsigned idx)
61+
: Mask(SM), Entries(E), FileIdx(idx) {};
5862

5963
SanitizerMask Mask;
6064
SectionEntries &Entries;
65+
unsigned FileIdx;
6166
};
6267

6368
std::vector<SanitizerSection> SanitizerSections;

‎clang/lib/AST/ItaniumMangle.cpp

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -455,7 +455,8 @@ class CXXNameMangler {
455455
void mangleSeqID(unsigned SeqID);
456456
void mangleName(GlobalDecl GD);
457457
void mangleType(QualType T);
458-
void mangleCXXRecordDecl(const CXXRecordDecl *Record);
458+
void mangleCXXRecordDecl(const CXXRecordDecl *Record,
459+
bool SuppressSubstitution = false);
459460
void mangleLambdaSig(const CXXRecordDecl *Lambda);
460461
void mangleModuleNamePrefix(StringRef Name, bool IsPartition = false);
461462
void mangleVendorQualifier(StringRef Name);
@@ -3103,11 +3104,12 @@ void CXXNameMangler::mangleType(QualType T) {
31033104
addSubstitution(T);
31043105
}
31053106

3106-
void CXXNameMangler::mangleCXXRecordDecl(const CXXRecordDecl *Record) {
3107+
void CXXNameMangler::mangleCXXRecordDecl(const CXXRecordDecl *Record,
3108+
bool SuppressSubstitution) {
31073109
if (mangleSubstitution(Record))
31083110
return;
31093111
mangleName(Record);
3110-
if (isCompatibleWith(LangOptions::ClangABI::Ver19))
3112+
if (SuppressSubstitution)
31113113
return;
31123114
addSubstitution(Record);
31133115
}
@@ -7557,7 +7559,12 @@ void ItaniumMangleContextImpl::mangleCXXCtorVTable(const CXXRecordDecl *RD,
75577559
// <special-name> ::= TC <type> <offset number> _ <base type>
75587560
CXXNameMangler Mangler(*this, Out);
75597561
Mangler.getStream() << "_ZTC";
7560-
Mangler.mangleCXXRecordDecl(RD);
7562+
// Older versions of clang did not add the record as a substitution candidate
7563+
// here.
7564+
bool SuppressSubstitution =
7565+
getASTContext().getLangOpts().getClangABICompat() <=
7566+
LangOptions::ClangABI::Ver19;
7567+
Mangler.mangleCXXRecordDecl(RD, SuppressSubstitution);
75617568
Mangler.getStream() << Offset;
75627569
Mangler.getStream() << '_';
75637570
Mangler.mangleCXXRecordDecl(Type);

‎clang/lib/Basic/NoSanitizeList.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,13 +44,11 @@ bool NoSanitizeList::containsFunction(SanitizerMask Mask,
4444

4545
bool NoSanitizeList::containsFile(SanitizerMask Mask, StringRef FileName,
4646
StringRef Category) const {
47-
unsigned NoSanLine = SSCL->inSectionBlame(Mask, "src", FileName, Category);
48-
if (NoSanLine == 0)
47+
auto NoSan = SSCL->inSectionBlame(Mask, "src", FileName, Category);
48+
if (NoSan == llvm::SpecialCaseList::NotFound)
4949
return false;
50-
unsigned SanLine = SSCL->inSectionBlame(Mask, "src", FileName, "sanitize");
51-
// If we have two cases such as `src:a.cpp=sanitize` and `src:a.cpp`, the
52-
// current entry override the previous entry.
53-
return !SanLine || NoSanLine > SanLine;
50+
auto San = SSCL->inSectionBlame(Mask, "src", FileName, "sanitize");
51+
return San == llvm::SpecialCaseList::NotFound || NoSan > San;
5452
}
5553

5654
bool NoSanitizeList::containsMainFile(SanitizerMask Mask, StringRef FileName,

‎clang/lib/Basic/SanitizerSpecialCaseList.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,27 +50,27 @@ void SanitizerSpecialCaseList::createSanitizerSections() {
5050
#undef SANITIZER
5151
#undef SANITIZER_GROUP
5252

53-
SanitizerSections.emplace_back(Mask, S.Entries);
53+
SanitizerSections.emplace_back(Mask, S.Entries, S.FileIdx);
5454
}
5555
}
5656

5757
bool SanitizerSpecialCaseList::inSection(SanitizerMask Mask, StringRef Prefix,
5858
StringRef Query,
5959
StringRef Category) const {
60-
return inSectionBlame(Mask, Prefix, Query, Category);
60+
return inSectionBlame(Mask, Prefix, Query, Category) != NotFound;
6161
}
6262

63-
unsigned SanitizerSpecialCaseList::inSectionBlame(SanitizerMask Mask,
64-
StringRef Prefix,
65-
StringRef Query,
66-
StringRef Category) const {
63+
std::pair<unsigned, unsigned>
64+
SanitizerSpecialCaseList::inSectionBlame(SanitizerMask Mask, StringRef Prefix,
65+
StringRef Query,
66+
StringRef Category) const {
6767
for (const auto &S : llvm::reverse(SanitizerSections)) {
6868
if (S.Mask & Mask) {
69-
unsigned lineNum =
69+
unsigned LineNum =
7070
SpecialCaseList::inSectionBlame(S.Entries, Prefix, Query, Category);
71-
if (lineNum > 0)
72-
return lineNum;
71+
if (LineNum > 0)
72+
return {S.FileIdx, LineNum};
7373
}
7474
}
75-
return 0;
75+
return NotFound;
7676
}

‎clang/lib/CIR/Dialect/IR/CIRDialect.cpp

Lines changed: 24 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@
1717

1818
#include "mlir/Interfaces/ControlFlowInterfaces.h"
1919
#include "mlir/Interfaces/FunctionImplementation.h"
20-
#include "mlir/Support/LogicalResult.h"
2120

2221
#include "clang/CIR/Dialect/IR/CIROpsDialect.cpp.inc"
2322
#include "clang/CIR/Dialect/IR/CIROpsEnums.cpp.inc"
@@ -1427,15 +1426,32 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
14271426
//===----------------------------------------------------------------------===//
14281427
LogicalResult cir::ShiftOp::verify() {
14291428
mlir::Operation *op = getOperation();
1430-
mlir::Type resType = getResult().getType();
1431-
const bool isOp0Vec = mlir::isa<cir::VectorType>(op->getOperand(0).getType());
1432-
const bool isOp1Vec = mlir::isa<cir::VectorType>(op->getOperand(1).getType());
1433-
if (isOp0Vec != isOp1Vec)
1429+
auto op0VecTy = mlir::dyn_cast<cir::VectorType>(op->getOperand(0).getType());
1430+
auto op1VecTy = mlir::dyn_cast<cir::VectorType>(op->getOperand(1).getType());
1431+
if (!op0VecTy ^ !op1VecTy)
14341432
return emitOpError() << "input types cannot be one vector and one scalar";
1435-
if (isOp1Vec && op->getOperand(1).getType() != resType) {
1436-
return emitOpError() << "shift amount must have the type of the result "
1437-
<< "if it is vector shift";
1433+
1434+
if (op0VecTy) {
1435+
if (op0VecTy.getSize() != op1VecTy.getSize())
1436+
return emitOpError() << "input vector types must have the same size";
1437+
1438+
auto opResultTy = mlir::dyn_cast<cir::VectorType>(getResult().getType());
1439+
if (!opResultTy)
1440+
return emitOpError() << "the type of the result must be a vector "
1441+
<< "if it is vector shift";
1442+
1443+
auto op0VecEleTy = mlir::cast<cir::IntType>(op0VecTy.getElementType());
1444+
auto op1VecEleTy = mlir::cast<cir::IntType>(op1VecTy.getElementType());
1445+
if (op0VecEleTy.getWidth() != op1VecEleTy.getWidth())
1446+
return emitOpError()
1447+
<< "vector operands do not have the same elements sizes";
1448+
1449+
auto resVecEleTy = mlir::cast<cir::IntType>(opResultTy.getElementType());
1450+
if (op0VecEleTy.getWidth() != resVecEleTy.getWidth())
1451+
return emitOpError() << "vector operands and result type do not have the "
1452+
"same elements sizes";
14381453
}
1454+
14391455
return mlir::success();
14401456
}
14411457

‎clang/lib/Driver/Driver.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5362,11 +5362,11 @@ void Driver::BuildJobs(Compilation &C) const {
53625362
});
53635363
}
53645364

5365-
// If the user passed -Qunused-arguments or there were errors, don't warn
5366-
// about any unused arguments.
5367-
if (Diags.hasErrorOccurred() ||
5368-
C.getArgs().hasArg(options::OPT_Qunused_arguments))
5369-
return;
5365+
// If the user passed -Qunused-arguments or there were errors, don't
5366+
// warn about any unused arguments.
5367+
bool ReportUnusedArguments =
5368+
!Diags.hasErrorOccurred() &&
5369+
!C.getArgs().hasArg(options::OPT_Qunused_arguments);
53705370

53715371
// Claim -fdriver-only here.
53725372
(void)C.getArgs().hasArg(options::OPT_fdriver_only);
@@ -5420,7 +5420,7 @@ void Driver::BuildJobs(Compilation &C) const {
54205420
!C.getActions().empty()) {
54215421
Diag(diag::err_drv_unsupported_opt_for_target)
54225422
<< A->getSpelling() << getTargetTriple();
5423-
} else {
5423+
} else if (ReportUnusedArguments) {
54245424
Diag(clang::diag::warn_drv_unused_argument)
54255425
<< A->getAsString(C.getArgs());
54265426
}

‎clang/lib/Sema/SemaTemplateDeductionGuide.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1099,6 +1099,10 @@ BuildDeductionGuideForTypeAlias(Sema &SemaRef,
10991099
// parameters, used for building `TemplateArgsForBuildingFPrime`.
11001100
SmallVector<TemplateArgument, 16> TransformedDeducedAliasArgs(
11011101
AliasTemplate->getTemplateParameters()->size());
1102+
// We might be already within a pack expansion, but rewriting template
1103+
// parameters is independent of that. (We may or may not expand new packs
1104+
// when rewriting. So clear the state)
1105+
Sema::ArgPackSubstIndexRAII PackSubstReset(SemaRef, std::nullopt);
11021106

11031107
for (unsigned AliasTemplateParamIdx : DeducedAliasTemplateParams) {
11041108
auto *TP =

‎clang/test/CIR/CodeGen/vector-ext.cpp

Lines changed: 55 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -461,6 +461,61 @@ void foo9() {
461461
// OGCG: %[[SHR:.*]] = ashr <4 x i32> %[[TMP_A]], %[[TMP_B]]
462462
// OGCG: store <4 x i32> %[[SHR]], ptr %[[SHR_RES]], align 16
463463

464+
void foo10() {
465+
vi4 a = {1, 2, 3, 4};
466+
uvi4 b = {5u, 6u, 7u, 8u};
467+
468+
vi4 shl = a << b;
469+
uvi4 shr = b >> a;
470+
}
471+
472+
// CIR: %[[VEC_A:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init]
473+
// CIR: %[[VEC_B:.*]] = cir.alloca !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>, ["b", init]
474+
// CIR: %[[SHL_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["shl", init]
475+
// CIR: %[[SHR_RES:.*]] = cir.alloca !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>, ["shr", init]
476+
// CIR: %[[VEC_A_VAL:.*]] = cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i>
477+
// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
478+
// CIR: %[[VEC_B_VAL:.*]] = cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !u32i, !u32i, !u32i, !u32i) : !cir.vector<4 x !u32i>
479+
// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
480+
// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
481+
// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
482+
// CIR: %[[SHL:.*]] = cir.shift(left, %[[TMP_A]] : !cir.vector<4 x !s32i>, %[[TMP_B]] : !cir.vector<4 x !u32i>) -> !cir.vector<4 x !s32i>
483+
// CIR: cir.store{{.*}} %[[SHL]], %[[SHL_RES]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
484+
// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
485+
// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
486+
// CIR: %[[SHR:.*]] = cir.shift(right, %[[TMP_B]] : !cir.vector<4 x !u32i>, %[[TMP_A]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !u32i>
487+
// CIR: cir.store{{.*}} %[[SHR]], %[[SHR_RES]] : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
488+
489+
// LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16
490+
// LLVM: %[[VEC_B:.*]] = alloca <4 x i32>, i64 1, align 16
491+
// LLVM: %[[SHL_RES:.*]] = alloca <4 x i32>, i64 1, align 16
492+
// LLVM: %[[SHR_RES:.*]] = alloca <4 x i32>, i64 1, align 16
493+
// LLVM: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %[[VEC_A]], align 16
494+
// LLVM: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %[[VEC_B]], align 16
495+
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
496+
// LLVM: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
497+
// LLVM: %[[SHL:.*]] = shl <4 x i32> %[[TMP_A]], %[[TMP_B]]
498+
// LLVM: store <4 x i32> %[[SHL]], ptr %[[SHL_RES]], align 16
499+
// LLVM: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
500+
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
501+
// LLVM: %[[SHR:.*]] = lshr <4 x i32> %[[TMP_B]], %[[TMP_A]]
502+
// LLVM: store <4 x i32> %[[SHR]], ptr %[[SHR_RES]], align 16
503+
504+
// OGCG: %[[VEC_A:.*]] = alloca <4 x i32>, align 16
505+
// OGCG: %[[VEC_B:.*]] = alloca <4 x i32>, align 16
506+
// OGCG: %[[SHL_RES:.*]] = alloca <4 x i32>, align 16
507+
// OGCG: %[[SHR_RES:.*]] = alloca <4 x i32>, align 16
508+
// OGCG: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %[[VEC_A]], align 16
509+
// OGCG: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %[[VEC_B]], align 16
510+
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
511+
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
512+
// OGCG: %[[SHL:.*]] = shl <4 x i32> %[[TMP_A]], %[[TMP_B]]
513+
// OGCG: store <4 x i32> %[[SHL]], ptr %[[SHL_RES]], align 16
514+
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
515+
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
516+
// OGCG: %[[SHR:.*]] = lshr <4 x i32> %[[TMP_B]], %[[TMP_A]]
517+
// OGCG: store <4 x i32> %[[SHR]], ptr %[[SHR_RES]], align 16
518+
464519
void foo11() {
465520
vi4 a = {1, 2, 3, 4};
466521
vi4 b = {5, 6, 7, 8};
@@ -933,4 +988,3 @@ void foo14() {
933988
// OGCG: %[[TMP_B:.*]] = load <4 x float>, ptr %[[VEC_B]], align 16
934989
// OGCG: %[[GE:.*]] = fcmp oge <4 x float> %[[TMP_A]], %[[TMP_B]]
935990
// OGCG: %[[RES:.*]] = sext <4 x i1> %[[GE]] to <4 x i32>
936-

‎clang/test/CIR/CodeGen/vector.cpp

Lines changed: 57 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -396,19 +396,9 @@ void foo9() {
396396
// CIR: %[[VEC_B:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init]
397397
// CIR: %[[SHL_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["shl", init]
398398
// CIR: %[[SHR_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["shr", init]
399-
// CIR: %[[CONST_1:.*]] = cir.const #cir.int<1> : !s32i
400-
// CIR: %[[CONST_2:.*]] = cir.const #cir.int<2> : !s32i
401-
// CIR: %[[CONST_3:.*]] = cir.const #cir.int<3> : !s32i
402-
// CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i
403-
// CIR: %[[VEC_A_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] :
404-
// CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i>
399+
// CIR: %[[VEC_A_VAL:.*]] = cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i>
405400
// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
406-
// CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i
407-
// CIR: %[[CONST_6:.*]] = cir.const #cir.int<6> : !s32i
408-
// CIR: %[[CONST_7:.*]] = cir.const #cir.int<7> : !s32i
409-
// CIR: %[[CONST_8:.*]] = cir.const #cir.int<8> : !s32i
410-
// CIR: %[[VEC_B_VAL:.*]] = cir.vec.create(%[[CONST_5]], %[[CONST_6]], %[[CONST_7]], %[[CONST_8]] :
411-
// CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i>
401+
// CIR: %[[VEC_B_VAL:.*]] = cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i>
412402
// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
413403
// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
414404
// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
@@ -449,6 +439,61 @@ void foo9() {
449439
// OGCG: %[[SHR:.*]] = ashr <4 x i32> %[[TMP_A]], %[[TMP_B]]
450440
// OGCG: store <4 x i32> %[[SHR]], ptr %[[SHR_RES]], align 16
451441

442+
void foo10() {
443+
vi4 a = {1, 2, 3, 4};
444+
uvi4 b = {5u, 6u, 7u, 8u};
445+
446+
vi4 shl = a << b;
447+
uvi4 shr = b >> a;
448+
}
449+
450+
// CIR: %[[VEC_A:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init]
451+
// CIR: %[[VEC_B:.*]] = cir.alloca !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>, ["b", init]
452+
// CIR: %[[SHL_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["shl", init]
453+
// CIR: %[[SHR_RES:.*]] = cir.alloca !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>, ["shr", init]
454+
// CIR: %[[VEC_A_VAL:.*]] = cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i>
455+
// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
456+
// CIR: %[[VEC_B_VAL:.*]] = cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !u32i, !u32i, !u32i, !u32i) : !cir.vector<4 x !u32i>
457+
// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
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// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
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// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
460+
// CIR: %[[SHL:.*]] = cir.shift(left, %[[TMP_A]] : !cir.vector<4 x !s32i>, %[[TMP_B]] : !cir.vector<4 x !u32i>) -> !cir.vector<4 x !s32i>
461+
// CIR: cir.store{{.*}} %[[SHL]], %[[SHL_RES]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
462+
// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
463+
// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
464+
// CIR: %[[SHR:.*]] = cir.shift(right, %[[TMP_B]] : !cir.vector<4 x !u32i>, %[[TMP_A]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !u32i>
465+
// CIR: cir.store{{.*}} %[[SHR]], %[[SHR_RES]] : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
466+
467+
// LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16
468+
// LLVM: %[[VEC_B:.*]] = alloca <4 x i32>, i64 1, align 16
469+
// LLVM: %[[SHL_RES:.*]] = alloca <4 x i32>, i64 1, align 16
470+
// LLVM: %[[SHR_RES:.*]] = alloca <4 x i32>, i64 1, align 16
471+
// LLVM: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %[[VEC_A]], align 16
472+
// LLVM: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %[[VEC_B]], align 16
473+
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
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// LLVM: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
475+
// LLVM: %[[SHL:.*]] = shl <4 x i32> %[[TMP_A]], %[[TMP_B]]
476+
// LLVM: store <4 x i32> %[[SHL]], ptr %[[SHL_RES]], align 16
477+
// LLVM: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
478+
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
479+
// LLVM: %[[SHR:.*]] = lshr <4 x i32> %[[TMP_B]], %[[TMP_A]]
480+
// LLVM: store <4 x i32> %[[SHR]], ptr %[[SHR_RES]], align 16
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482+
// OGCG: %[[VEC_A:.*]] = alloca <4 x i32>, align 16
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// OGCG: %[[VEC_B:.*]] = alloca <4 x i32>, align 16
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// OGCG: %[[SHL_RES:.*]] = alloca <4 x i32>, align 16
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// OGCG: %[[SHR_RES:.*]] = alloca <4 x i32>, align 16
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// OGCG: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %[[VEC_A]], align 16
487+
// OGCG: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %[[VEC_B]], align 16
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// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
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// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
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// OGCG: %[[SHL:.*]] = shl <4 x i32> %[[TMP_A]], %[[TMP_B]]
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// OGCG: store <4 x i32> %[[SHL]], ptr %[[SHL_RES]], align 16
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// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
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// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
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// OGCG: %[[SHR:.*]] = lshr <4 x i32> %[[TMP_B]], %[[TMP_A]]
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// OGCG: store <4 x i32> %[[SHR]], ptr %[[SHR_RES]], align 16
496+
452497
void foo11() {
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vi4 a = {1, 2, 3, 4};
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vi4 b = {5, 6, 7, 8};

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