@@ -306,7 +306,7 @@ def IIT_TRUNC_ARG : IIT_Base<26>;
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def IIT_ANYPTR : IIT_Base<27>;
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def IIT_V1 : IIT_Vec<1, 28>;
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def IIT_VARARG : IIT_VT<isVoid, 29>;
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- def IIT_HALF_VEC_ARG : IIT_Base<30>;
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+ def IIT_ONE_NTH_ELTS_VEC_ARG : IIT_Base<30>;
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def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
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def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
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def IIT_I128 : IIT_Int<128, 35>;
@@ -335,14 +335,8 @@ def IIT_I4 : IIT_Int<4, 58>;
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def IIT_AARCH64_SVCOUNT : IIT_VT<aarch64svcount, 59>;
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def IIT_V6 : IIT_Vec<6, 60>;
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def IIT_V10 : IIT_Vec<10, 61>;
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- def IIT_ONE_THIRD_VEC_ARG : IIT_Base<62>;
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- def IIT_ONE_FIFTH_VEC_ARG : IIT_Base<63>;
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- def IIT_ONE_SEVENTH_VEC_ARG : IIT_Base<64>;
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- def IIT_V2048: IIT_Vec<2048, 65>;
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- def IIT_V4096: IIT_Vec<4096, 66>;
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- def IIT_ONE_FOURTH_VEC_ARG : IIT_Base<67>;
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- def IIT_ONE_SIXTH_VEC_ARG : IIT_Base<68>;
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- def IIT_ONE_EIGHTH_VEC_ARG : IIT_Base<69>;
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+ def IIT_V2048: IIT_Vec<2048, 62>;
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+ def IIT_V4096: IIT_Vec<4096, 63>;
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}
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defvar IIT_all_FixedTypes = !filter(iit, IIT_all,
@@ -479,27 +473,15 @@ class LLVMVectorOfAnyPointersToElt<int num>
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class LLVMVectorElementType<int num> : LLVMMatchType<num, IIT_VEC_ELEMENT>;
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// Match the type of another intrinsic parameter that is expected to be a
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- // vector type, but change the element count to be half as many.
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- class LLVMHalfElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_HALF_VEC_ARG>;
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-
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- class LLVMOneThirdElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_ONE_THIRD_VEC_ARG>;
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-
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- class LLVMOneFourthElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_ONE_FOURTH_VEC_ARG>;
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-
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- class LLVMOneFifthElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_ONE_FIFTH_VEC_ARG>;
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-
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- class LLVMOneSixthElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_ONE_SIXTH_VEC_ARG>;
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-
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- class LLVMOneSeventhElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_ONE_SEVENTH_VEC_ARG>;
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-
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- class LLVMOneEighthElementsVectorType<int num>
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- : LLVMMatchType<num, IIT_ONE_EIGHTH_VEC_ARG>;
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+ // vector type, but change the element count to be 1/n of it.
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+ class LLVMOneNthElementsVectorType<int idx, int n>
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+ : LLVMMatchType<idx, IIT_ONE_NTH_ELTS_VEC_ARG> {
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+ let Sig = [
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+ IIT_ONE_NTH_ELTS_VEC_ARG.Number,
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+ EncNextArgN<idx>.ret,
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+ n,
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+ ];
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+ }
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// Match the type of another intrinsic parameter that is expected to be a
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// vector type (i.e. <N x iM>) but with each element subdivided to
@@ -2770,118 +2752,15 @@ def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[llvm_anyvector_ty, llvm_i64_ty],
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[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
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+ foreach n = 2...8 in {
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+ def int_vector_interleave#n : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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+ !listsplat(LLVMOneNthElementsVectorType<0, n>, n),
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+ [IntrNoMem]>;
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- def int_vector_interleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMHalfElementsVectorType<0>,
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- LLVMHalfElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>,
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- LLVMHalfElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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-
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- def int_vector_interleave3 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMOneThirdElementsVectorType<0>,
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- LLVMOneThirdElementsVectorType<0>,
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- LLVMOneThirdElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave3 : DefaultAttrsIntrinsic<[LLVMOneThirdElementsVectorType<0>,
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- LLVMOneThirdElementsVectorType<0>,
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- LLVMOneThirdElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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-
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- def int_vector_interleave4 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMOneFourthElementsVectorType<0>,
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- LLVMOneFourthElementsVectorType<0>,
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- LLVMOneFourthElementsVectorType<0>,
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- LLVMOneFourthElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave4 : DefaultAttrsIntrinsic<[LLVMOneFourthElementsVectorType<0>,
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- LLVMOneFourthElementsVectorType<0>,
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- LLVMOneFourthElementsVectorType<0>,
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- LLVMOneFourthElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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-
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- def int_vector_interleave5 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave5 : DefaultAttrsIntrinsic<[LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>,
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- LLVMOneFifthElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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-
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- def int_vector_interleave6 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave6 : DefaultAttrsIntrinsic<[LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>,
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- LLVMOneSixthElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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-
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- def int_vector_interleave7 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave7 : DefaultAttrsIntrinsic<[LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>,
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- LLVMOneSeventhElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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-
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- def int_vector_interleave8 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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- [LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>],
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- [IntrNoMem]>;
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-
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- def int_vector_deinterleave8 : DefaultAttrsIntrinsic<[LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>,
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- LLVMOneEighthElementsVectorType<0>],
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- [llvm_anyvector_ty],
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- [IntrNoMem]>;
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+ def int_vector_deinterleave#n : DefaultAttrsIntrinsic<!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
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+ [llvm_anyvector_ty],
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+ [IntrNoMem]>;
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+ }
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//===-------------- Intrinsics to perform partial reduction ---------------===//
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