Skip to content

Commit e50b4de

Browse files
author
Tony Varghese
committed
[NFC][PowerpC] Add testcases for locking down the instruction support for ternary operators
1 parent 062d24a commit e50b4de

File tree

4 files changed

+721
-0
lines changed

4 files changed

+721
-0
lines changed

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll

Lines changed: 200 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,200 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
3+
4+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
5+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
6+
7+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
8+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
9+
10+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
11+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
12+
13+
; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
14+
define <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
15+
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32:
16+
; CHECK: # %bb.0: # %entry
17+
; CHECK-NEXT: xxleqv v5, v5, v5
18+
; CHECK-NEXT: xxlxor vs0, v3, v4
19+
; CHECK-NEXT: xxland vs1, v3, v4
20+
; CHECK-NEXT: vslw v2, v2, v5
21+
; CHECK-NEXT: vsraw v2, v2, v5
22+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
23+
; CHECK-NEXT: blr
24+
entry:
25+
%xor = xor <4 x i32> %B, %C
26+
%and = and <4 x i32> %B, %C
27+
%res = select <4 x i1> %A, <4 x i32> %xor, <4 x i32> %and
28+
ret <4 x i32> %res
29+
}
30+
31+
; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
32+
define <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
33+
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: xxlxor v5, v5, v5
36+
; CHECK-NEXT: xxlxor vs0, v3, v4
37+
; CHECK-NEXT: xxland vs1, v3, v4
38+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
39+
; CHECK-NEXT: vsld v2, v2, v5
40+
; CHECK-NEXT: vsrad v2, v2, v5
41+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
42+
; CHECK-NEXT: blr
43+
entry:
44+
%xor = xor <2 x i64> %B, %C
45+
%and = and <2 x i64> %B, %C
46+
%res = select <2 x i1> %A, <2 x i64> %xor, <2 x i64> %and
47+
ret <2 x i64> %res
48+
}
49+
50+
; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
51+
define <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
52+
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
53+
; CHECK: # %bb.0: # %entry
54+
; CHECK-NEXT: xxleqv v5, v5, v5
55+
; CHECK-NEXT: xxlnor vs0, v3, v4
56+
; CHECK-NEXT: xxland vs1, v3, v4
57+
; CHECK-NEXT: vslw v2, v2, v5
58+
; CHECK-NEXT: vsraw v2, v2, v5
59+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
60+
; CHECK-NEXT: blr
61+
entry:
62+
%or = or <4 x i32> %B, %C
63+
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
64+
%and = and <4 x i32> %B, %C
65+
%res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %and
66+
ret <4 x i32> %res
67+
}
68+
69+
; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
70+
define <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
71+
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
72+
; CHECK: # %bb.0: # %entry
73+
; CHECK-NEXT: xxlxor v5, v5, v5
74+
; CHECK-NEXT: xxlnor vs0, v3, v4
75+
; CHECK-NEXT: xxland vs1, v3, v4
76+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
77+
; CHECK-NEXT: vsld v2, v2, v5
78+
; CHECK-NEXT: vsrad v2, v2, v5
79+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
80+
; CHECK-NEXT: blr
81+
entry:
82+
%or = or <2 x i64> %B, %C
83+
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
84+
%and = and <2 x i64> %B, %C
85+
%res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %and
86+
ret <2 x i64> %res
87+
}
88+
89+
; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
90+
define <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
91+
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32:
92+
; CHECK: # %bb.0: # %entry
93+
; CHECK-NEXT: xxleqv v5, v5, v5
94+
; CHECK-NEXT: xxleqv vs0, v3, v4
95+
; CHECK-NEXT: xxland vs1, v3, v4
96+
; CHECK-NEXT: vslw v2, v2, v5
97+
; CHECK-NEXT: vsraw v2, v2, v5
98+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
99+
; CHECK-NEXT: blr
100+
entry:
101+
%xor = xor <4 x i32> %B, %C
102+
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
103+
%and = and <4 x i32> %B, %C
104+
%res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %and
105+
ret <4 x i32> %res
106+
}
107+
108+
; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
109+
define <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
110+
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
111+
; CHECK: # %bb.0: # %entry
112+
; CHECK-NEXT: xxlxor v5, v5, v5
113+
; CHECK-NEXT: xxleqv vs0, v3, v4
114+
; CHECK-NEXT: xxland vs1, v3, v4
115+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
116+
; CHECK-NEXT: vsld v2, v2, v5
117+
; CHECK-NEXT: vsrad v2, v2, v5
118+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
119+
; CHECK-NEXT: blr
120+
entry:
121+
%xor = xor <2 x i64> %B, %C
122+
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
123+
%and = and <2 x i64> %B, %C
124+
%res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %and
125+
ret <2 x i64> %res
126+
}
127+
128+
; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
129+
define <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
130+
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32:
131+
; CHECK: # %bb.0: # %entry
132+
; CHECK-NEXT: xxleqv v5, v5, v5
133+
; CHECK-NEXT: xxlnor vs0, v4, v4
134+
; CHECK-NEXT: xxland vs1, v3, v4
135+
; CHECK-NEXT: vslw v2, v2, v5
136+
; CHECK-NEXT: vsraw v2, v2, v5
137+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
138+
; CHECK-NEXT: blr
139+
entry:
140+
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
141+
%and = and <4 x i32> %B, %C
142+
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
143+
ret <4 x i32> %res
144+
}
145+
146+
; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
147+
define <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
148+
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
149+
; CHECK: # %bb.0: # %entry
150+
; CHECK-NEXT: xxlxor v5, v5, v5
151+
; CHECK-NEXT: xxlnor vs0, v4, v4
152+
; CHECK-NEXT: xxland vs1, v3, v4
153+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
154+
; CHECK-NEXT: vsld v2, v2, v5
155+
; CHECK-NEXT: vsrad v2, v2, v5
156+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
157+
; CHECK-NEXT: blr
158+
entry:
159+
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
160+
%and = and <2 x i64> %B, %C
161+
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
162+
ret <2 x i64> %res
163+
}
164+
165+
; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
166+
define <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
167+
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32:
168+
; CHECK: # %bb.0: # %entry
169+
; CHECK-NEXT: xxleqv v5, v5, v5
170+
; CHECK-NEXT: xxlnor vs0, v3, v3
171+
; CHECK-NEXT: xxland vs1, v3, v4
172+
; CHECK-NEXT: vslw v2, v2, v5
173+
; CHECK-NEXT: vsraw v2, v2, v5
174+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
175+
; CHECK-NEXT: blr
176+
entry:
177+
%not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
178+
%and = and <4 x i32> %B, %C
179+
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
180+
ret <4 x i32> %res
181+
}
182+
183+
; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
184+
define <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
185+
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
186+
; CHECK: # %bb.0: # %entry
187+
; CHECK-NEXT: xxlxor v5, v5, v5
188+
; CHECK-NEXT: xxlnor vs0, v3, v3
189+
; CHECK-NEXT: xxland vs1, v3, v4
190+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
191+
; CHECK-NEXT: vsld v2, v2, v5
192+
; CHECK-NEXT: vsrad v2, v2, v5
193+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
194+
; CHECK-NEXT: blr
195+
entry:
196+
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
197+
%and = and <2 x i64> %B, %C
198+
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
199+
ret <2 x i64> %res
200+
}

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll

Lines changed: 182 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,182 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
3+
4+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
5+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
6+
7+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
8+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
9+
10+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
11+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
12+
13+
; Function to test ternary(A, and(B, C), B) for <4 x i32>
14+
define <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
15+
; CHECK-LABEL: ternary_A_and_BC_B_4x32:
16+
; CHECK: # %bb.0: # %entry
17+
; CHECK-NEXT: xxleqv v5, v5, v5
18+
; CHECK-NEXT: xxland vs0, v3, v4
19+
; CHECK-NEXT: vslw v2, v2, v5
20+
; CHECK-NEXT: vsraw v2, v2, v5
21+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
22+
; CHECK-NEXT: blr
23+
entry:
24+
%and = and <4 x i32> %B, %C
25+
%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %B
26+
ret <4 x i32> %res
27+
}
28+
29+
; Function to test ternary(A, and(B, C), B) for <2 x i64>
30+
define <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
31+
; CHECK-LABEL: ternary_A_and_BC_B_2x64:
32+
; CHECK: # %bb.0: # %entry
33+
; CHECK-NEXT: xxlxor v5, v5, v5
34+
; CHECK-NEXT: xxland vs0, v3, v4
35+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
36+
; CHECK-NEXT: vsld v2, v2, v5
37+
; CHECK-NEXT: vsrad v2, v2, v5
38+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
39+
; CHECK-NEXT: blr
40+
entry:
41+
%and = and <2 x i64> %B, %C
42+
%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %B
43+
ret <2 x i64> %res
44+
}
45+
46+
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
47+
define <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
48+
; CHECK-LABEL: ternary_A_nor_BC_B_4x32:
49+
; CHECK: # %bb.0: # %entry
50+
; CHECK-NEXT: xxleqv v5, v5, v5
51+
; CHECK-NEXT: xxlnor vs0, v3, v4
52+
; CHECK-NEXT: vslw v2, v2, v5
53+
; CHECK-NEXT: vsraw v2, v2, v5
54+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
55+
; CHECK-NEXT: blr
56+
entry:
57+
%or = or <4 x i32> %B, %C
58+
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
59+
%res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %B
60+
ret <4 x i32> %res
61+
}
62+
63+
; Function to test ternary(A, nor(B, C), B) for <2 x i64>
64+
define <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
65+
; CHECK-LABEL: ternary_A_nor_BC_B_2x64:
66+
; CHECK: # %bb.0: # %entry
67+
; CHECK-NEXT: xxlxor v5, v5, v5
68+
; CHECK-NEXT: xxlnor vs0, v3, v4
69+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
70+
; CHECK-NEXT: vsld v2, v2, v5
71+
; CHECK-NEXT: vsrad v2, v2, v5
72+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
73+
; CHECK-NEXT: blr
74+
entry:
75+
%or = or <2 x i64> %B, %C
76+
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
77+
%res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %B
78+
ret <2 x i64> %res
79+
}
80+
81+
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
82+
define <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
83+
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32:
84+
; CHECK: # %bb.0: # %entry
85+
; CHECK-NEXT: xxleqv v5, v5, v5
86+
; CHECK-NEXT: xxleqv vs0, v3, v4
87+
; CHECK-NEXT: vslw v2, v2, v5
88+
; CHECK-NEXT: vsraw v2, v2, v5
89+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
90+
; CHECK-NEXT: blr
91+
entry:
92+
%xor = xor <4 x i32> %B, %C
93+
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
94+
%res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %B
95+
ret <4 x i32> %res
96+
}
97+
98+
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
99+
define <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
100+
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64:
101+
; CHECK: # %bb.0: # %entry
102+
; CHECK-NEXT: xxlxor v5, v5, v5
103+
; CHECK-NEXT: xxleqv vs0, v3, v4
104+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
105+
; CHECK-NEXT: vsld v2, v2, v5
106+
; CHECK-NEXT: vsrad v2, v2, v5
107+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
108+
; CHECK-NEXT: blr
109+
entry:
110+
%xor = xor <2 x i64> %B, %C
111+
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
112+
%res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %B
113+
ret <2 x i64> %res
114+
}
115+
116+
; Function to test ternary(A, not(C), B) for <4 x i32>
117+
define <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
118+
; CHECK-LABEL: ternary_A_not_C_B_4x32:
119+
; CHECK: # %bb.0: # %entry
120+
; CHECK-NEXT: xxleqv v5, v5, v5
121+
; CHECK-NEXT: xxlnor vs0, v4, v4
122+
; CHECK-NEXT: vslw v2, v2, v5
123+
; CHECK-NEXT: vsraw v2, v2, v5
124+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
125+
; CHECK-NEXT: blr
126+
entry:
127+
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
128+
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %B
129+
ret <4 x i32> %res
130+
}
131+
132+
; Function to test ternary(A, not(C), B) for <2 x i64>
133+
define <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
134+
; CHECK-LABEL: ternary_A_not_C_B_2x64:
135+
; CHECK: # %bb.0: # %entry
136+
; CHECK-NEXT: xxlxor v5, v5, v5
137+
; CHECK-NEXT: xxlnor vs0, v4, v4
138+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
139+
; CHECK-NEXT: vsld v2, v2, v5
140+
; CHECK-NEXT: vsrad v2, v2, v5
141+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
142+
; CHECK-NEXT: blr
143+
entry:
144+
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
145+
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %B
146+
ret <2 x i64> %res
147+
}
148+
149+
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
150+
define <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
151+
; CHECK-LABEL: ternary_A_nand_BC_B_4x32:
152+
; CHECK: # %bb.0: # %entry
153+
; CHECK-NEXT: xxleqv v5, v5, v5
154+
; CHECK-NEXT: xxlnand vs0, v3, v4
155+
; CHECK-NEXT: vslw v2, v2, v5
156+
; CHECK-NEXT: vsraw v2, v2, v5
157+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
158+
; CHECK-NEXT: blr
159+
entry:
160+
%and = and <4 x i32> %B, %C
161+
%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
162+
%res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %B
163+
ret <4 x i32> %res
164+
}
165+
166+
; Function to test ternary(A, nand(B, C), B) for <2 x i64>
167+
define <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
168+
; CHECK-LABEL: ternary_A_nand_BC_B_2x64:
169+
; CHECK: # %bb.0: # %entry
170+
; CHECK-NEXT: xxlxor v5, v5, v5
171+
; CHECK-NEXT: xxlnand vs0, v3, v4
172+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
173+
; CHECK-NEXT: vsld v2, v2, v5
174+
; CHECK-NEXT: vsrad v2, v2, v5
175+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
176+
; CHECK-NEXT: blr
177+
entry:
178+
%and = and <2 x i64> %B, %C
179+
%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
180+
%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %B
181+
ret <2 x i64> %res
182+
}

0 commit comments

Comments
 (0)