[RISCV] Can we teach RISCVectorPeephole to commute FMA to fold vmerge?

[topperc]

We have special isel patterns like VPatFPMulAccVL_VV_VF_RM and VPatMultiplyAccVL_VV_VX that look for riscv_vmerge_vl and an fma or mul+add. Can improve RISCVectorPeephole to remove these patterns?

CC: @lukel97 @preames

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Craig Topper (topperc)

We have special isel patterns like `VPatFPMulAccVL_VV_VF_RM` and `VPatMultiplyAccVL_VV_VX` that look for riscv_vmerge_vl and an fma or mul+add. Can improve RISCVectorPeephole to remove these patterns?

CC: @lukel97 @preames

[topperc]

@lukel97 is the code for merge vmerge into arithmetic ops still in RISCVISelDAGToDAG.cpp and not RISCVectorPeephole?

[lukel97]

Can improve RISCVectorPeephole to remove these patterns?

Probably, it's a good place for anything related to vmerge pseudos.

@lukel97 is the code for merge vmerge into arithmetic ops still in RISCVISelDAGToDAG.cpp and not RISCVectorPeephole?

Yeah, I've been meaning to move performCombineVMergeAndVOps over but it fell through the cracks. I think it was difficult the last time I tried because of the physical V0 copies but it might be easier now that masks are virtual registers. I'll try to give it another stab this week.