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[RISCV] Permutation intrinsics in Zvfhmin unnecessarily require Zvfh #143975

@dzaima

Description

@dzaima

Basic 16-bit float permutation intrinsics (vslideup / vslidedown / vrgather), which can be in Zvfhmin (as they need just the vfloat16* type and a basic e16 Zve32x instruction), unnecessarily also require Zvfh.

This happens both with __attribute__((target)): https://riscvc.godbolt.org/z/x6nnb6YoG
and with -march: https://riscvc.godbolt.org/z/b4dMrda3e

Copied-out code sample that should work but doesn't, for reference:

#include<riscv_vector.h>

__attribute__((target("arch=+v,+zvfhmin")))
vfloat16m1_t vrgather(vfloat16m1_t op1, vuint16m1_t index, size_t vl) {
    return __riscv_vrgatherei16_vv_f16m1(op1, index, vl);
}

__attribute__((target("arch=+v,+zvfhmin")))
vfloat16m1_t vslideup(vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
    return __riscv_vslideup_vx_f16m1(dest, src, offset, vl);
}

__attribute__((target("arch=+v,+zvfhmin")))
vfloat16m1_t vslidedown(vfloat16m1_t src, size_t offset, size_t vl) {
    return __riscv_vslidedown_vx_f16m1(src, offset, vl);
}

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