AMDGPU: Add baseline tests for #139317 #140607

arsenm · 2025-05-19T20:06:24Z

No description provided.

arsenm · 2025-05-19T20:06:37Z

This stack of pull requests is managed by Graphite. Learn more about stacking.

llvmbot · 2025-05-19T20:06:53Z

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Patch is 43.52 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/140607.diff

5 Files Affected:

(added) llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir (+320)
(modified) llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir (+387-5)
(added) llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll (+66)
(added) llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir (+202)
(modified) llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir (+26)

diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
new file mode 100644
index 0000000000000..3021761f099fa
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
@@ -0,0 +1,320 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name: v_mov_b64_pseudo_imm_0_copy_to_areg_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_copy_to_areg_64
+    ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[V_MOV_B]]
+    ; GCN-NEXT: $agpr0_agpr1 = COPY [[COPY]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %1:areg_64_align2 = COPY %0
+    $agpr0_agpr1 = COPY %1
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_neg1_copy_to_areg_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_neg1_copy_to_areg_64
+    ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO -1, implicit $exec
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[V_MOV_B]]
+    ; GCN-NEXT: $agpr0_agpr1 = COPY [[COPY]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO -1, implicit $exec
+    %1:areg_64_align2 = COPY %0
+    $agpr0_agpr1 = COPY %1
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_literal_copy_to_areg_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_literal_copy_to_areg_64
+    ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 999, implicit $exec
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[V_MOV_B]]
+    ; GCN-NEXT: $agpr0_agpr1 = COPY [[COPY]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 999, implicit $exec
+    %1:areg_64_align2 = COPY %0
+    $agpr0_agpr1 = COPY %1
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_0_copy_sub0_to_agpr_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_copy_sub0_to_agpr_32
+    ; GCN: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; GCN-NEXT: $agpr0 = COPY [[V_ACCVGPR_WRITE_B32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %1:agpr_32 = COPY %0.sub0
+    $agpr0 = COPY %1
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_0_copy_sub1_to_agpr_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_copy_sub1_to_agpr_32
+    ; GCN: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; GCN-NEXT: $agpr0 = COPY [[V_ACCVGPR_WRITE_B32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %1:agpr_32 = COPY %0.sub1
+    $agpr0 = COPY %1
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_lit_copy_sub0_to_agpr_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_lit_copy_sub0_to_agpr_32
+    ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B]].sub0
+    ; GCN-NEXT: $agpr0 = COPY [[COPY]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    %1:agpr_32 = COPY %0.sub0
+    $agpr0 = COPY %1
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_lit_copy_sub1_to_agpr_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_lit_copy_sub1_to_agpr_32
+    ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B]].sub1
+    ; GCN-NEXT: $agpr0 = COPY [[COPY]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    %1:agpr_32 = COPY %0.sub1
+    $agpr0 = COPY %1
+    S_ENDPGM 0
+
+...
+
+
+---
+name: v_mov_b64_pseudo_imm_0_copy_to_av_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_copy_to_av_64
+    ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[V_MOV_B]]
+    ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
+    %0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %1:av_64_align2 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
+
+
+# XXX need f64 use
+
+
+
+
+---
+name: v_mov_b64_pseudo_imm_0_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, 0, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp64_1_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp64_1_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, 4607182418800017408, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_lit_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_lit_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, [[V_MOV_B]], 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp32_1_splat_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp32_1_splat_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, [[V_MOV_B]], 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub0_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub0_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, 1065353216, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    %2:vgpr_32 = COPY %1.sub0
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub1_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub1_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, 1065353216, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    %2:vgpr_32 = COPY %1.sub1
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp64_1_copy_extract_sub0_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp64_1_copy_extract_sub0_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, 0, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
+    %2:vgpr_32 = COPY %1.sub0
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp64_1_copy_extract_sub1_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp64_1_copy_extract_sub1_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248, implicit $exec
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
+    %2:vgpr_32 = COPY %1.sub1
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
index 1f15066264c74..cfb42de4456f3 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefixes=GCN,GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefixes=GCN,GFX9 %s
 
 ---
 name:            no_fold_fp_64bit_literal_sgpr
@@ -41,10 +42,16 @@ tracksRegLiveness: true
 body:             |
   bb.0:
 
-    ; GCN-LABEL: name: fold_fp_32bit_literal_sgpr
-    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
-    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, 4636737291354636288, 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
+    ; GFX10-LABEL: name: fold_fp_32bit_literal_sgpr
+    ; GFX10: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GFX10-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, 4636737291354636288, 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
+    ;
+    ; GFX9-LABEL: name: fold_fp_32bit_literal_sgpr
+    ; GFX9: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GFX9-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4636737291354636288
+    ; GFX9-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[S_MOV_B]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
+    ; GFX9-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
     %0:vreg_64 = IMPLICIT_DEF
     %1:sreg_64 = S_MOV_B64_IMM_PSEUDO 4636737291354636288
     %2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
@@ -136,3 +143,378 @@ body:             |
     %2:vreg_64 = V_PK_ADD_F32 0, %0, 0, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
     SI_RETURN_TO_EPILOG %2
 ...
+
+---
+name: v_mov_b64_pseudo_imm_0_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, 0, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp64_1_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp64_1_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, 4607182418800017408, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_lit_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_lit_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, [[V_MOV_B]], 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp32_1_splat_full_copy_to_f64_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0_vgpr1
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp32_1_splat_full_copy_to_f64_use
+    ; GCN: liveins: $vgpr0_vgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    ; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, [[V_MOV_B]], 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    %2:vreg_64_align2 = COPY %1
+    %3:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0_vgpr1 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub0_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub0_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, 1065353216, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    %2:vgpr_32 = COPY %1.sub0
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub1_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp32_1_splat_copy_extract_sub1_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, 1065353216, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
+    %2:vgpr_32 = COPY %1.sub1
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp64_1_copy_extract_sub0_to_f32_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+  liveins: $vgpr0
+    ; GCN-LABEL: name: v_mov_b64_pseudo_imm_fp64_1_copy_extract_sub0_to_f32_use
+    ; GCN: liveins: $vgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, 0, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_]]
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vreg_64_align2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
+    %2:vgpr_32 = COPY %1.sub0
+    %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %0, 1, %2, 0, 0, implicit $mode, implicit $exec
+    $vgpr0 = COPY %3
+    S_ENDPGM 0
+
+...
+
+---
+name: v_mov_b64_pseudo_imm_fp...
[truncated]

arsenm · 2025-05-27T10:12:03Z

ping

arsenm · 2025-05-29T17:28:59Z

Merge activity

May 29, 5:28 PM UTC: A user started a stack merge that includes this pull request via Graphite.
May 29, 5:39 PM UTC: Graphite rebased this pull request as part of a merge.
May 29, 5:41 PM UTC: @arsenm merged this pull request with Graphite.

arsenm mentioned this pull request May 19, 2025

AMDGPU: Remove redundant operand folding checks #140587

Merged

arsenm added the backend:AMDGPU label May 19, 2025 — with Graphite App

arsenm requested review from jayfoad and kosarev May 19, 2025 20:06

arsenm mentioned this pull request May 19, 2025

AMDGPU: Delete seemingly dead s_fmaak_f32/s_fmamk_f32 folding code #140580

Merged

arsenm requested review from mbrkusanin and Sisyph May 19, 2025 20:06

arsenm mentioned this pull request May 19, 2025

AMDGPU: Fix tracking subreg defs when folding through reg_sequence #140608

Open

arsenm marked this pull request as ready for review May 19, 2025 20:06

arsenm force-pushed the users/arsenm/issue139317/add-baseline-test branch from 4021541 to ad698bf Compare May 21, 2025 10:01

arsenm force-pushed the users/arsenm/amdgpu/remove-redundant-operand-legality-checks branch from 04c0bfd to a372f44 Compare May 21, 2025 10:01

arsenm mentioned this pull request May 21, 2025

AMDGPU: Handle folding vector splats of inline split f64 inline immediates #140878

Open

arsenm force-pushed the users/arsenm/amdgpu/remove-redundant-operand-legality-checks branch from a372f44 to 93c2961 Compare May 27, 2025 12:39

arsenm force-pushed the users/arsenm/issue139317/add-baseline-test branch from ad698bf to 8a6cb7b Compare May 27, 2025 12:39

arsenm force-pushed the users/arsenm/amdgpu/remove-redundant-operand-legality-checks branch from 93c2961 to d71c838 Compare May 27, 2025 16:02

arsenm force-pushed the users/arsenm/issue139317/add-baseline-test branch from 8a6cb7b to 999939f Compare May 27, 2025 16:02

arsenm force-pushed the users/arsenm/amdgpu/remove-redundant-operand-legality-checks branch from d71c838 to a8db1cb Compare May 29, 2025 17:36

Base automatically changed from users/arsenm/amdgpu/remove-redundant-operand-legality-checks to main May 29, 2025 17:38

AMDGPU: Add baseline tests for #139317

6deba1d

arsenm force-pushed the users/arsenm/issue139317/add-baseline-test branch from 999939f to 6deba1d Compare May 29, 2025 17:39

arsenm merged commit a239900 into main May 29, 2025
6 of 9 checks passed

arsenm deleted the users/arsenm/issue139317/add-baseline-test branch May 29, 2025 17:41

svkeerthy pushed a commit that referenced this pull request May 29, 2025

AMDGPU: Add baseline tests for #139317 (#140607)

ca5b52f

google-yfyang pushed a commit to google-yfyang/llvm-project that referenced this pull request May 29, 2025

AMDGPU: Add baseline tests for llvm#139317 (llvm#140607)

1693cae

sivan-shani pushed a commit to sivan-shani/llvm-project that referenced this pull request Jun 3, 2025

AMDGPU: Add baseline tests for llvm#139317 (llvm#140607)

cca8eae

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

AMDGPU: Add baseline tests for #139317 #140607

AMDGPU: Add baseline tests for #139317 #140607

Uh oh!

arsenm commented May 19, 2025

Uh oh!

arsenm commented May 19, 2025 •

edited

Loading

Uh oh!

llvmbot commented May 19, 2025

Uh oh!

arsenm commented May 27, 2025

Uh oh!

arsenm commented May 29, 2025 •

edited

Loading

Uh oh!

Uh oh!

Uh oh!

AMDGPU: Add baseline tests for #139317 #140607

AMDGPU: Add baseline tests for #139317 #140607

Uh oh!

Conversation

arsenm commented May 19, 2025

Uh oh!

arsenm commented May 19, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

llvmbot commented May 19, 2025

Uh oh!

arsenm commented May 27, 2025

Uh oh!

arsenm commented May 29, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Merge activity

Uh oh!

Uh oh!

Uh oh!

arsenm commented May 19, 2025 •

edited

Loading

arsenm commented May 29, 2025 •

edited

Loading