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[AMDGPU][Scheduler] Delete RescheduleRegions bitvector from scheduler (NFC) #141595

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Merged
merged 1 commit into from
May 27, 2025
Merged

[AMDGPU][Scheduler] Delete RescheduleRegions bitvector from scheduler (NFC) #141595

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18 changes: 4 additions & 14 deletions llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -937,12 +937,10 @@ void GCNScheduleDAGMILive::finalizeSchedule() {
// GCNScheduleDAGMILive::schedule().
LiveIns.resize(Regions.size());
Pressure.resize(Regions.size());
RescheduleRegions.resize(Regions.size());
RegionsWithHighRP.resize(Regions.size());
RegionsWithExcessRP.resize(Regions.size());
RegionsWithMinOcc.resize(Regions.size());
RegionsWithIGLPInstrs.resize(Regions.size());
RescheduleRegions.set();
RegionsWithHighRP.reset();
RegionsWithExcessRP.reset();
RegionsWithMinOcc.reset();
Expand Down Expand Up @@ -1236,10 +1234,7 @@ bool ClusteredLowOccStage::initGCNRegion() {
}

bool PreRARematStage::initGCNRegion() {
if (!DAG.RescheduleRegions[RegionIdx])
return false;

return GCNSchedStage::initGCNRegion();
return RescheduleRegions[RegionIdx] && GCNSchedStage::initGCNRegion();
}

void GCNSchedStage::setupNewBlock() {
Expand All @@ -1258,7 +1253,6 @@ void GCNSchedStage::setupNewBlock() {

void GCNSchedStage::finalizeGCNRegion() {
DAG.Regions[RegionIdx] = std::pair(DAG.RegionBegin, DAG.RegionEnd);
DAG.RescheduleRegions[RegionIdx] = false;
if (S.HasHighPressure)
DAG.RegionsWithHighRP[RegionIdx] = true;

Expand All @@ -1271,7 +1265,7 @@ void GCNSchedStage::finalizeGCNRegion() {
SavedMutations.swap(DAG.Mutations);

DAG.exitRegion();
RegionIdx++;
advanceRegion();
}

void GCNSchedStage::checkScheduling() {
Expand Down Expand Up @@ -1332,10 +1326,9 @@ void GCNSchedStage::checkScheduling() {
unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF);

if (PressureAfter.getVGPRNum(ST.hasGFX90AInsts()) > MaxVGPRs ||
PressureAfter.getVGPRNum(false) > MaxArchVGPRs ||
PressureAfter.getArchVGPRNum() > MaxArchVGPRs ||
PressureAfter.getAGPRNum() > MaxArchVGPRs ||
PressureAfter.getSGPRNum() > MaxSGPRs) {
DAG.RescheduleRegions[RegionIdx] = true;
DAG.RegionsWithHighRP[RegionIdx] = true;
DAG.RegionsWithExcessRP[RegionIdx] = true;
}
Expand Down Expand Up @@ -1577,9 +1570,6 @@ void GCNSchedStage::revertScheduling() {
DAG.RegionsWithMinOcc[RegionIdx] =
PressureBefore.getOccupancy(ST) == DAG.MinOccupancy;
LLVM_DEBUG(dbgs() << "Attempting to revert scheduling.\n");
DAG.RescheduleRegions[RegionIdx] =
S.hasNextStage() &&
S.getNextStage() != GCNSchedStageID::UnclusteredHighRPReschedule;
DAG.RegionEnd = DAG.RegionBegin;
int SkippedDebugInstr = 0;
for (MachineInstr *MI : Unsched) {
Expand Down Expand Up @@ -2154,7 +2144,7 @@ void PreRARematStage::rematerialize() {
AchievedOcc = TargetOcc;
for (auto &[I, OriginalRP] : ImpactedRegions) {
bool IsEmptyRegion = DAG.Regions[I].first == DAG.Regions[I].second;
DAG.RescheduleRegions[I] = !IsEmptyRegion;
RescheduleRegions[I] = !IsEmptyRegion;
if (!RecomputeRP.contains(I))
continue;

Expand Down
9 changes: 4 additions & 5 deletions llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
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Original file line number Diff line number Diff line change
Expand Up @@ -243,10 +243,6 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive {
// Vector of regions recorder for later rescheduling
SmallVector<RegionBoundaries, 32> Regions;

// Records if a region is not yet scheduled, or schedule has been reverted,
// or we generally desire to reschedule it.
BitVector RescheduleRegions;

// Record regions with high register pressure.
BitVector RegionsWithHighRP;

Expand Down Expand Up @@ -476,6 +472,9 @@ class PreRARematStage : public GCNSchedStage {
/// In case we need to rollback rematerializations, save lane masks for all
/// rematerialized registers in all regions in which they are live-ins.
DenseMap<std::pair<unsigned, Register>, LaneBitmask> RegMasks;
/// After successful stage initialization, indicates which regions should be
/// rescheduled.
BitVector RescheduleRegions;
/// Target occupancy the stage estimates is reachable through
/// rematerialization. Greater than or equal to the pre-stage min occupancy.
unsigned TargetOcc;
Expand Down Expand Up @@ -520,7 +519,7 @@ class PreRARematStage : public GCNSchedStage {
bool shouldRevertScheduling(unsigned WavesAfter) override;

PreRARematStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
: GCNSchedStage(StageID, DAG) {}
: GCNSchedStage(StageID, DAG), RescheduleRegions(DAG.Regions.size()) {}
};

class ILPInitialScheduleStage : public GCNSchedStage {
Expand Down