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[RISCV] Add bltu/bgeu zero => bnez/beqz canonicalisation to RISCVInstrInfo::simplifyInstruction #141775

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Merged
merged 1 commit into from
May 29, 2025
Merged

[RISCV] Add bltu/bgeu zero => bnez/beqz canonicalisation to RISCVInstrInfo::simplifyInstruction #141775

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18 changes: 18 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4191,6 +4191,24 @@ bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
return true;
}
break;
case RISCV::BLTU:
// bltu zero, rs, imm => bne rs, zero, imm
if (MI.getOperand(0).getReg() == RISCV::X0) {
MachineOperand MO0 = MI.getOperand(0);
MI.removeOperand(0);
MI.insert(MI.operands_begin() + 1, {MO0});
MI.setDesc(get(RISCV::BNE));
}
break;
case RISCV::BGEU:
// bgeu zero, rs, imm => beq rs, zero, imm
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Thinking about other cases here:

bgeu rs, zero, imm is an unconditionally taken branch. Rewriting as a unconditional branch is hard (due to CFG updates), but maybe we could turn this into beq zero, zero, imm? That would remove the register use, and might compress better?

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beq zero, zero, imm isn't compressible. The first register needs to be x8-x15.

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Yes, bgeu reg, zero is on my radar and as you say the CFG update makes it challenging. I hadn't considered canonicalising to beq zero, zero, imm. beq reg, reg, imm would be an alternative that has the chance of being compressible.

There are ~440 static instances of bgeu reg, zero in an RVA22 test-suite build. 40 instances of beq with rs1 == rs2 and 50 of bne with rs1 == rs2.

if (MI.getOperand(0).getReg() == RISCV::X0) {
MachineOperand MO0 = MI.getOperand(0);
MI.removeOperand(0);
MI.insert(MI.operands_begin() + 1, {MO0});
MI.setDesc(get(RISCV::BEQ));
}
break;
}
return false;
}
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36 changes: 36 additions & 0 deletions llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
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Expand Up @@ -742,3 +742,39 @@ body: |
renamable $x10 = MAXU renamable $x11, renamable $x11
PseudoRET implicit $x10
...
---
name: bltu
body: |
; CHECK-LABEL: name: bltu
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x11 = COPY $x12
; CHECK-NEXT: BNE $x12, $x0, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: PseudoRET
bb.0:
renamable $x11 = COPY $x12
BLTU $x0, renamable $x11, %bb.1
bb.1:
PseudoRET
...
---
name: bgeu
body: |
; CHECK-LABEL: name: bgeu
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x11 = COPY $x12
; CHECK-NEXT: BEQ $x12, $x0, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: PseudoRET
bb.0:
renamable $x11 = COPY $x12
BGEU $x0, renamable $x11, %bb.1
bb.1:
PseudoRET
...
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