AMDGPU: Add is_fpclass to isBoolSGPR

[arsenm]

No description provided.

[arsenm]

• AMDGPU: Add is.shared/is.private intrinsics to isBoolSGPR #141804
• AMDGPU: Add overflow operations to isBoolSGPR #141803
• AMDGPU: Add is_fpclass to isBoolSGPR #141801 👈 (View in Graphite)
• main

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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/141801.diff

2 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+1)
• (modified) llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll (+25)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ade88a16193b8..c9fd2948d669f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11908,6 +11908,7 @@ bool llvm::isBoolSGPR(SDValue V) {
   default:
     break;
   case ISD::SETCC:
+  case ISD::IS_FPCLASS:
   case AMDGPUISD::FP_CLASS:
     return true;
   case ISD::AND:
diff --git a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
index b763bec89eef3..bdad6f40480d3 100644
--- a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
@@ -20,6 +20,31 @@ bb:
   ret void
 }
 
+; GCN-LABEL: {{^}}and_sext_bool_fcmp:
+; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GCN-NEXT: s_setpc_b64
+define i32 @and_sext_bool_fcmp(float %x, i32 %y) {
+  %cmp = fcmp oeq float %x, 0.0
+  %sext = sext i1 %cmp to i32
+  %and = and i32 %sext, %y
+  ret i32 %and
+}
+
+; GCN-LABEL: {{^}}and_sext_bool_fpclass:
+; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b
+; GCN-NEXT: v_cmp_class_f32_e32 vcc, v0, [[K]]
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GCN-NEXT: s_setpc_b64
+define i32 @and_sext_bool_fpclass(float %x, i32 %y) {
+  %class = call i1 @llvm.is.fpclass(float %x, i32 123)
+  %sext = sext i1 %class to i32
+  %and = and i32 %sext, %y
+  ret i32 %and
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 declare i32 @llvm.amdgcn.workitem.id.y() #0

[arsenm]

Merge activity

• May 28, 7:25 PM UTC: A user started a stack merge that includes this pull request via Graphite.
• May 28, 7:27 PM UTC: Graphite rebased this pull request as part of a merge.
• May 28, 7:29 PM UTC: Graphite rebased this pull request as part of a merge.
• May 28, 7:31 PM UTC: @arsenm merged this pull request with Graphite.