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AMDGPU: Add is_fpclass to isBoolSGPR #141801

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Merged
merged 1 commit into from
May 28, 2025
Merged

AMDGPU: Add is_fpclass to isBoolSGPR #141801

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11901,6 +11901,7 @@ bool llvm::isBoolSGPR(SDValue V) {
default:
break;
case ISD::SETCC:
case ISD::IS_FPCLASS:
case AMDGPUISD::FP_CLASS:
return true;
case ISD::AND:
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25 changes: 25 additions & 0 deletions llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
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Expand Up @@ -20,6 +20,31 @@ bb:
ret void
}

; GCN-LABEL: {{^}}and_sext_bool_fcmp:
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GCN-NEXT: s_setpc_b64
define i32 @and_sext_bool_fcmp(float %x, i32 %y) {
%cmp = fcmp oeq float %x, 0.0
%sext = sext i1 %cmp to i32
%and = and i32 %sext, %y
ret i32 %and
}

; GCN-LABEL: {{^}}and_sext_bool_fpclass:
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b
; GCN-NEXT: v_cmp_class_f32_e32 vcc, v0, [[K]]
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GCN-NEXT: s_setpc_b64
define i32 @and_sext_bool_fpclass(float %x, i32 %y) {
%class = call i1 @llvm.is.fpclass(float %x, i32 123)
%sext = sext i1 %class to i32
%and = and i32 %sext, %y
ret i32 %and
}

declare i32 @llvm.amdgcn.workitem.id.x() #0

declare i32 @llvm.amdgcn.workitem.id.y() #0
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