[MISched] Add templates for creating custom schedulers #141935
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-backend-aarch64 Author: Pengcheng Wang (wangpc-pp) ChangesWe make This can simplify some code for targets that have custom scheduler Full diff: https://github.com/llvm/llvm-project/pull/141935.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index b15abf040058e..d1b5b83e5300b 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1349,14 +1349,6 @@ class PostGenericScheduler : public GenericSchedulerBase {
void pickNodeFromQueue(SchedBoundary &Zone, SchedCandidate &Cand);
};
-/// Create the standard converging machine scheduler. This will be used as the
-/// default scheduler if the target does not set a default.
-/// Adds default DAG mutations.
-ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C);
-
-/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
-ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C);
-
/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
std::unique_ptr<ScheduleDAGMutation>
@@ -1375,6 +1367,41 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
+/// Create the standard converging machine scheduler. This will be used as the
+/// default scheduler if the target does not set a default.
+/// Adds default DAG mutations.
+template <typename Strategy = GenericScheduler>
+ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C) {
+ ScheduleDAGMILive *DAG =
+ new ScheduleDAGMILive(C, std::make_unique<Strategy>(C));
+ // Register DAG post-processors.
+ //
+ // FIXME: extend the mutation API to allow earlier mutations to instantiate
+ // data and pass it to later mutations. Have a single mutation that gathers
+ // the interesting nodes in one pass.
+ DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+
+ const TargetSubtargetInfo &STI = C->MF->getSubtarget();
+ // Add MacroFusion mutation if fusions are not empty.
+ const auto &MacroFusions = STI.getMacroFusions();
+ if (!MacroFusions.empty())
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
+ return DAG;
+}
+
+/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
+template <typename Strategy = PostGenericScheduler>
+ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C) {
+ ScheduleDAGMI *DAG = new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
+ /*RemoveKillFlags=*/true);
+ const TargetSubtargetInfo &STI = C->MF->getSubtarget();
+ // Add MacroFusion mutation if fusions are not empty.
+ const auto &MacroFusions = STI.getMacroFusions();
+ if (!MacroFusions.empty())
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
+ return DAG;
+}
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 9b2862de22b69..0c6dcb3a04494 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3848,26 +3848,6 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}
-/// Create the standard converging machine scheduler. This will be used as the
-/// default scheduler if the target does not set a default.
-ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
- ScheduleDAGMILive *DAG =
- new ScheduleDAGMILive(C, std::make_unique<GenericScheduler>(C));
- // Register DAG post-processors.
- //
- // FIXME: extend the mutation API to allow earlier mutations to instantiate
- // data and pass it to later mutations. Have a single mutation that gathers
- // the interesting nodes in one pass.
- DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
-
- const TargetSubtargetInfo &STI = C->MF->getSubtarget();
- // Add MacroFusion mutation if fusions are not empty.
- const auto &MacroFusions = STI.getMacroFusions();
- if (!MacroFusions.empty())
- DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
- return DAG;
-}
-
static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
return createGenericSchedLive(C);
}
@@ -4140,18 +4120,6 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}
-ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
- ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, std::make_unique<PostGenericScheduler>(C),
- /*RemoveKillFlags=*/true);
- const TargetSubtargetInfo &STI = C->MF->getSubtarget();
- // Add MacroFusion mutation if fusions are not empty.
- const auto &MacroFusions = STI.getMacroFusions();
- if (!MacroFusions.empty())
- DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
- return DAG;
-}
-
//===----------------------------------------------------------------------===//
// ILP Scheduler. Currently for experimental analysis of heuristics.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b6562..adee5309e816e 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -527,8 +527,7 @@ class AArch64PassConfig : public TargetPassConfig {
createPostMachineScheduler(MachineSchedContext *C) const override {
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
- /* RemoveKillFlags=*/true);
+ createGenericSchedPostRA<AArch64PostRASchedStrategy>(C);
if (ST.hasFusion()) {
// Run the Macro Fusion after RA again since literals are expanded from
// pseudos then (v. addPreSched2()).
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index cd188304595e1..2145c999ae522 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -317,9 +317,9 @@ getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
ScheduleDAGMILive *DAG =
- new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
- std::make_unique<PPCPreRASchedStrategy>(C) :
- std::make_unique<GenericScheduler>(C));
+ ST.usePPCPreRASchedStrategy()
+ ? createGenericSchedLive<PPCPreRASchedStrategy>(C)
+ : createGenericSchedLive<GenericScheduler>(C);
// add DAG Mutations here.
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasStoreFusion())
@@ -330,13 +330,12 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
return DAG;
}
-static ScheduleDAGInstrs *createPPCPostMachineScheduler(
- MachineSchedContext *C) {
+static ScheduleDAGInstrs *
+createPPCPostMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
- ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
- std::make_unique<PPCPostRASchedStrategy>(C) :
- std::make_unique<PostGenericScheduler>(C), true);
+ ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
+ ? createGenericSchedPostRA<PPCPostRASchedStrategy>(C)
+ : createGenericSchedPostRA<PostGenericScheduler>(C);
// add DAG Mutations here.
if (ST.hasStoreFusion())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index f76f41768e886..5a51f7e0e3fb6 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -219,9 +219,7 @@ class SystemZPassConfig : public TargetPassConfig {
ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext *C) const override {
- return new ScheduleDAGMI(C,
- std::make_unique<SystemZPostRASchedStrategy>(C),
- /*RemoveKillFlags=*/true);
+ return createGenericSchedPostRA<SystemZPostRASchedStrategy>(C);
}
void addIRPasses() override;
|
|
@llvm/pr-subscribers-backend-powerpc Author: Pengcheng Wang (wangpc-pp) ChangesWe make This can simplify some code for targets that have custom scheduler Full diff: https://github.com/llvm/llvm-project/pull/141935.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index b15abf040058e..d1b5b83e5300b 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1349,14 +1349,6 @@ class PostGenericScheduler : public GenericSchedulerBase {
void pickNodeFromQueue(SchedBoundary &Zone, SchedCandidate &Cand);
};
-/// Create the standard converging machine scheduler. This will be used as the
-/// default scheduler if the target does not set a default.
-/// Adds default DAG mutations.
-ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C);
-
-/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
-ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C);
-
/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
std::unique_ptr<ScheduleDAGMutation>
@@ -1375,6 +1367,41 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
+/// Create the standard converging machine scheduler. This will be used as the
+/// default scheduler if the target does not set a default.
+/// Adds default DAG mutations.
+template <typename Strategy = GenericScheduler>
+ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C) {
+ ScheduleDAGMILive *DAG =
+ new ScheduleDAGMILive(C, std::make_unique<Strategy>(C));
+ // Register DAG post-processors.
+ //
+ // FIXME: extend the mutation API to allow earlier mutations to instantiate
+ // data and pass it to later mutations. Have a single mutation that gathers
+ // the interesting nodes in one pass.
+ DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+
+ const TargetSubtargetInfo &STI = C->MF->getSubtarget();
+ // Add MacroFusion mutation if fusions are not empty.
+ const auto &MacroFusions = STI.getMacroFusions();
+ if (!MacroFusions.empty())
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
+ return DAG;
+}
+
+/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
+template <typename Strategy = PostGenericScheduler>
+ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C) {
+ ScheduleDAGMI *DAG = new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
+ /*RemoveKillFlags=*/true);
+ const TargetSubtargetInfo &STI = C->MF->getSubtarget();
+ // Add MacroFusion mutation if fusions are not empty.
+ const auto &MacroFusions = STI.getMacroFusions();
+ if (!MacroFusions.empty())
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
+ return DAG;
+}
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 9b2862de22b69..0c6dcb3a04494 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3848,26 +3848,6 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}
-/// Create the standard converging machine scheduler. This will be used as the
-/// default scheduler if the target does not set a default.
-ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
- ScheduleDAGMILive *DAG =
- new ScheduleDAGMILive(C, std::make_unique<GenericScheduler>(C));
- // Register DAG post-processors.
- //
- // FIXME: extend the mutation API to allow earlier mutations to instantiate
- // data and pass it to later mutations. Have a single mutation that gathers
- // the interesting nodes in one pass.
- DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
-
- const TargetSubtargetInfo &STI = C->MF->getSubtarget();
- // Add MacroFusion mutation if fusions are not empty.
- const auto &MacroFusions = STI.getMacroFusions();
- if (!MacroFusions.empty())
- DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
- return DAG;
-}
-
static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
return createGenericSchedLive(C);
}
@@ -4140,18 +4120,6 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}
-ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
- ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, std::make_unique<PostGenericScheduler>(C),
- /*RemoveKillFlags=*/true);
- const TargetSubtargetInfo &STI = C->MF->getSubtarget();
- // Add MacroFusion mutation if fusions are not empty.
- const auto &MacroFusions = STI.getMacroFusions();
- if (!MacroFusions.empty())
- DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
- return DAG;
-}
-
//===----------------------------------------------------------------------===//
// ILP Scheduler. Currently for experimental analysis of heuristics.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b6562..adee5309e816e 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -527,8 +527,7 @@ class AArch64PassConfig : public TargetPassConfig {
createPostMachineScheduler(MachineSchedContext *C) const override {
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
- /* RemoveKillFlags=*/true);
+ createGenericSchedPostRA<AArch64PostRASchedStrategy>(C);
if (ST.hasFusion()) {
// Run the Macro Fusion after RA again since literals are expanded from
// pseudos then (v. addPreSched2()).
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index cd188304595e1..2145c999ae522 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -317,9 +317,9 @@ getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
ScheduleDAGMILive *DAG =
- new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
- std::make_unique<PPCPreRASchedStrategy>(C) :
- std::make_unique<GenericScheduler>(C));
+ ST.usePPCPreRASchedStrategy()
+ ? createGenericSchedLive<PPCPreRASchedStrategy>(C)
+ : createGenericSchedLive<GenericScheduler>(C);
// add DAG Mutations here.
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasStoreFusion())
@@ -330,13 +330,12 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
return DAG;
}
-static ScheduleDAGInstrs *createPPCPostMachineScheduler(
- MachineSchedContext *C) {
+static ScheduleDAGInstrs *
+createPPCPostMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
- ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
- std::make_unique<PPCPostRASchedStrategy>(C) :
- std::make_unique<PostGenericScheduler>(C), true);
+ ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
+ ? createGenericSchedPostRA<PPCPostRASchedStrategy>(C)
+ : createGenericSchedPostRA<PostGenericScheduler>(C);
// add DAG Mutations here.
if (ST.hasStoreFusion())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index f76f41768e886..5a51f7e0e3fb6 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -219,9 +219,7 @@ class SystemZPassConfig : public TargetPassConfig {
ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext *C) const override {
- return new ScheduleDAGMI(C,
- std::make_unique<SystemZPostRASchedStrategy>(C),
- /*RemoveKillFlags=*/true);
+ return createGenericSchedPostRA<SystemZPostRASchedStrategy>(C);
}
void addIRPasses() override;
|
|
@llvm/pr-subscribers-backend-systemz Author: Pengcheng Wang (wangpc-pp) ChangesWe make This can simplify some code for targets that have custom scheduler Full diff: https://github.com/llvm/llvm-project/pull/141935.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index b15abf040058e..d1b5b83e5300b 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1349,14 +1349,6 @@ class PostGenericScheduler : public GenericSchedulerBase {
void pickNodeFromQueue(SchedBoundary &Zone, SchedCandidate &Cand);
};
-/// Create the standard converging machine scheduler. This will be used as the
-/// default scheduler if the target does not set a default.
-/// Adds default DAG mutations.
-ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C);
-
-/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
-ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C);
-
/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
std::unique_ptr<ScheduleDAGMutation>
@@ -1375,6 +1367,41 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
+/// Create the standard converging machine scheduler. This will be used as the
+/// default scheduler if the target does not set a default.
+/// Adds default DAG mutations.
+template <typename Strategy = GenericScheduler>
+ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C) {
+ ScheduleDAGMILive *DAG =
+ new ScheduleDAGMILive(C, std::make_unique<Strategy>(C));
+ // Register DAG post-processors.
+ //
+ // FIXME: extend the mutation API to allow earlier mutations to instantiate
+ // data and pass it to later mutations. Have a single mutation that gathers
+ // the interesting nodes in one pass.
+ DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+
+ const TargetSubtargetInfo &STI = C->MF->getSubtarget();
+ // Add MacroFusion mutation if fusions are not empty.
+ const auto &MacroFusions = STI.getMacroFusions();
+ if (!MacroFusions.empty())
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
+ return DAG;
+}
+
+/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
+template <typename Strategy = PostGenericScheduler>
+ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C) {
+ ScheduleDAGMI *DAG = new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
+ /*RemoveKillFlags=*/true);
+ const TargetSubtargetInfo &STI = C->MF->getSubtarget();
+ // Add MacroFusion mutation if fusions are not empty.
+ const auto &MacroFusions = STI.getMacroFusions();
+ if (!MacroFusions.empty())
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
+ return DAG;
+}
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 9b2862de22b69..0c6dcb3a04494 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3848,26 +3848,6 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}
-/// Create the standard converging machine scheduler. This will be used as the
-/// default scheduler if the target does not set a default.
-ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
- ScheduleDAGMILive *DAG =
- new ScheduleDAGMILive(C, std::make_unique<GenericScheduler>(C));
- // Register DAG post-processors.
- //
- // FIXME: extend the mutation API to allow earlier mutations to instantiate
- // data and pass it to later mutations. Have a single mutation that gathers
- // the interesting nodes in one pass.
- DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
-
- const TargetSubtargetInfo &STI = C->MF->getSubtarget();
- // Add MacroFusion mutation if fusions are not empty.
- const auto &MacroFusions = STI.getMacroFusions();
- if (!MacroFusions.empty())
- DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
- return DAG;
-}
-
static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
return createGenericSchedLive(C);
}
@@ -4140,18 +4120,6 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}
-ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
- ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, std::make_unique<PostGenericScheduler>(C),
- /*RemoveKillFlags=*/true);
- const TargetSubtargetInfo &STI = C->MF->getSubtarget();
- // Add MacroFusion mutation if fusions are not empty.
- const auto &MacroFusions = STI.getMacroFusions();
- if (!MacroFusions.empty())
- DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
- return DAG;
-}
-
//===----------------------------------------------------------------------===//
// ILP Scheduler. Currently for experimental analysis of heuristics.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b6562..adee5309e816e 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -527,8 +527,7 @@ class AArch64PassConfig : public TargetPassConfig {
createPostMachineScheduler(MachineSchedContext *C) const override {
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
- /* RemoveKillFlags=*/true);
+ createGenericSchedPostRA<AArch64PostRASchedStrategy>(C);
if (ST.hasFusion()) {
// Run the Macro Fusion after RA again since literals are expanded from
// pseudos then (v. addPreSched2()).
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index cd188304595e1..2145c999ae522 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -317,9 +317,9 @@ getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
ScheduleDAGMILive *DAG =
- new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
- std::make_unique<PPCPreRASchedStrategy>(C) :
- std::make_unique<GenericScheduler>(C));
+ ST.usePPCPreRASchedStrategy()
+ ? createGenericSchedLive<PPCPreRASchedStrategy>(C)
+ : createGenericSchedLive<GenericScheduler>(C);
// add DAG Mutations here.
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasStoreFusion())
@@ -330,13 +330,12 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
return DAG;
}
-static ScheduleDAGInstrs *createPPCPostMachineScheduler(
- MachineSchedContext *C) {
+static ScheduleDAGInstrs *
+createPPCPostMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
- ScheduleDAGMI *DAG =
- new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
- std::make_unique<PPCPostRASchedStrategy>(C) :
- std::make_unique<PostGenericScheduler>(C), true);
+ ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
+ ? createGenericSchedPostRA<PPCPostRASchedStrategy>(C)
+ : createGenericSchedPostRA<PostGenericScheduler>(C);
// add DAG Mutations here.
if (ST.hasStoreFusion())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index f76f41768e886..5a51f7e0e3fb6 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -219,9 +219,7 @@ class SystemZPassConfig : public TargetPassConfig {
ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext *C) const override {
- return new ScheduleDAGMI(C,
- std::make_unique<SystemZPostRASchedStrategy>(C),
- /*RemoveKillFlags=*/true);
+ return createGenericSchedPostRA<SystemZPostRASchedStrategy>(C);
}
void addIRPasses() override;
|
davemgreen
reviewed
May 29, 2025
mshockwave
reviewed
May 29, 2025
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Thanks for reminding! This was extracted from a downstream branch and I forgot to rebase. It's done now. |
davemgreen
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May 30, 2025
We rename `createGenericSchedLive` and `createGenericSchedPostRA` to `createSchedLive` and `createSchedPostRA`, and add a template parameter `Strategy` which is the generic implementation by default. This can simplify some code for targets that have custom scheduler strategy.
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sallto
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We rename `createGenericSchedLive` and `createGenericSchedPostRA` to `createSchedLive` and `createSchedPostRA`, and add a template parameter `Strategy` which is the generic implementation by default. This can simplify some code for targets that have custom scheduler strategy.
rorth
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We rename `createGenericSchedLive` and `createGenericSchedPostRA` to `createSchedLive` and `createSchedPostRA`, and add a template parameter `Strategy` which is the generic implementation by default. This can simplify some code for targets that have custom scheduler strategy.
DhruvSrivastavaX
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Jun 12, 2025
We rename `createGenericSchedLive` and `createGenericSchedPostRA` to `createSchedLive` and `createSchedPostRA`, and add a template parameter `Strategy` which is the generic implementation by default. This can simplify some code for targets that have custom scheduler strategy.
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We rename
createGenericSchedLiveandcreateGenericSchedPostRAto
createSchedLiveandcreateSchedPostRA, and add a templateparameter
Strategywhich is the generic implementation by default.This can simplify some code for targets that have custom scheduler
strategy.