Skip to content

[MISched] Add templates for creating custom schedulers #141935

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 3, 2025
Merged

[MISched] Add templates for creating custom schedulers #141935

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
45 changes: 36 additions & 9 deletions llvm/include/llvm/CodeGen/MachineScheduler.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@
//
// ScheduleDAGInstrs *<Target>TargetMachine::
// createMachineScheduler(MachineSchedContext *C) {
// ScheduleDAGMI *DAG = createGenericSchedLive(C);
// ScheduleDAGMI *DAG = createSchedLive(C);
// DAG->addMutation(new CustomDAGMutation(...));
// return DAG;
// }
Expand Down Expand Up @@ -1383,14 +1383,6 @@ class LLVM_ABI PostGenericScheduler : public GenericSchedulerBase {
void pickNodeFromQueue(SchedBoundary &Zone, SchedCandidate &Cand);
};

/// Create the standard converging machine scheduler. This will be used as the
/// default scheduler if the target does not set a default.
/// Adds default DAG mutations.
LLVM_ABI ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C);

/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
LLVM_ABI ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C);

/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
Expand All @@ -1409,6 +1401,41 @@ LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);

/// Create the standard converging machine scheduler. This will be used as the
/// default scheduler if the target does not set a default.
/// Adds default DAG mutations.
template <typename Strategy = GenericScheduler>
LLVM_ABI ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {
ScheduleDAGMILive *DAG =
new ScheduleDAGMILive(C, std::make_unique<Strategy>(C));
// Register DAG post-processors.
//
// FIXME: extend the mutation API to allow earlier mutations to instantiate
// data and pass it to later mutations. Have a single mutation that gathers
// the interesting nodes in one pass.
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));

const TargetSubtargetInfo &STI = C->MF->getSubtarget();
// Add MacroFusion mutation if fusions are not empty.
const auto &MacroFusions = STI.getMacroFusions();
if (!MacroFusions.empty())
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
return DAG;
}

/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
template <typename Strategy = PostGenericScheduler>
LLVM_ABI ScheduleDAGMI *createSchedPostRA(MachineSchedContext *C) {
ScheduleDAGMI *DAG = new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
/*RemoveKillFlags=*/true);
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
// Add MacroFusion mutation if fusions are not empty.
const auto &MacroFusions = STI.getMacroFusions();
if (!MacroFusions.empty())
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
return DAG;
}

class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
// FIXME: Remove this member once RegisterClassInfo is queryable as an
// analysis.
Expand Down
38 changes: 3 additions & 35 deletions llvm/lib/CodeGen/MachineScheduler.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -547,7 +547,7 @@ ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
return Scheduler;

// Default to GenericScheduler.
return createGenericSchedLive(this);
return createSchedLive(this);
}

bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
Expand Down Expand Up @@ -595,7 +595,7 @@ ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
return Scheduler;

// Default to GenericScheduler.
return createGenericSchedPostRA(this);
return createSchedPostRA(this);
}

bool PostMachineSchedulerImpl::run(MachineFunction &Func,
Expand Down Expand Up @@ -4273,28 +4273,8 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}

/// Create the standard converging machine scheduler. This will be used as the
/// default scheduler if the target does not set a default.
ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
ScheduleDAGMILive *DAG =
new ScheduleDAGMILive(C, std::make_unique<GenericScheduler>(C));
// Register DAG post-processors.
//
// FIXME: extend the mutation API to allow earlier mutations to instantiate
// data and pass it to later mutations. Have a single mutation that gathers
// the interesting nodes in one pass.
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));

const TargetSubtargetInfo &STI = C->MF->getSubtarget();
// Add MacroFusion mutation if fusions are not empty.
const auto &MacroFusions = STI.getMacroFusions();
if (!MacroFusions.empty())
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
return DAG;
}

static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
return createGenericSchedLive(C);
return createSchedLive(C);
}

static MachineSchedRegistry
Expand Down Expand Up @@ -4598,18 +4578,6 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
}

ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
ScheduleDAGMI *DAG =
new ScheduleDAGMI(C, std::make_unique<PostGenericScheduler>(C),
/*RemoveKillFlags=*/true);
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
// Add MacroFusion mutation if fusions are not empty.
const auto &MacroFusions = STI.getMacroFusions();
if (!MacroFusions.empty())
DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
return DAG;
}

//===----------------------------------------------------------------------===//
// ILP Scheduler. Currently for experimental analysis of heuristics.
//===----------------------------------------------------------------------===//
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -487,7 +487,7 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
ScheduleDAGInstrs *
AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
ScheduleDAGMILive *DAG = createSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasFusion())
Expand All @@ -498,9 +498,7 @@ AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
AArch64TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
ScheduleDAGMI *DAG =
new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
/* RemoveKillFlags=*/true);
ScheduleDAGMI *DAG = createSchedPostRA<AArch64PostRASchedStrategy>(C);
if (ST.hasFusion()) {
// Run the Macro Fusion after RA again since literals are expanded from
// pseudos then (v. addPreSched2()).
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -751,7 +751,7 @@ StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
llvm::ScheduleDAGInstrs *
AMDGPUTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
ScheduleDAGMILive *DAG = createSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
if (ST.shouldClusterStores())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -328,7 +328,7 @@ ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {

ScheduleDAGInstrs *
ARMBaseTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
ScheduleDAGMILive *DAG = createSchedLive(C);
// add DAG Mutations here.
const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
if (ST.hasFusion())
Expand All @@ -338,7 +338,7 @@ ARMBaseTargetMachine::createMachineScheduler(MachineSchedContext *C) const {

ScheduleDAGInstrs *
ARMBaseTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
ScheduleDAGMI *DAG = createSchedPostRA(C);
// add DAG Mutations here.
const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
if (ST.hasFusion())
Expand Down
19 changes: 8 additions & 11 deletions llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -310,12 +310,10 @@ getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,

static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
ScheduleDAGMILive *DAG =
new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
std::make_unique<PPCPreRASchedStrategy>(C) :
std::make_unique<GenericScheduler>(C));
ScheduleDAGMILive *DAG = ST.usePPCPreRASchedStrategy()
? createSchedLive<PPCPreRASchedStrategy>(C)
: createSchedLive<GenericScheduler>(C);
// add DAG Mutations here.
DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasStoreFusion())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasFusion())
Expand All @@ -324,13 +322,12 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
return DAG;
}

static ScheduleDAGInstrs *createPPCPostMachineScheduler(
MachineSchedContext *C) {
static ScheduleDAGInstrs *
createPPCPostMachineScheduler(MachineSchedContext *C) {
const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
ScheduleDAGMI *DAG =
new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
std::make_unique<PPCPostRASchedStrategy>(C) :
std::make_unique<PostGenericScheduler>(C), true);
ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
? createSchedPostRA<PPCPostRASchedStrategy>(C)
: createSchedPostRA<PostGenericScheduler>(C);
// add DAG Mutations here.
if (ST.hasStoreFusion())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -300,7 +300,7 @@ ScheduleDAGInstrs *
RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGMILive *DAG = nullptr;
if (EnableMISchedLoadStoreClustering) {
DAG = createGenericSchedLive(C);
DAG = createSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
DAG->addMutation(createStoreClusterDAGMutation(
Expand All @@ -309,7 +309,7 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {

const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
if (!DisableVectorMaskMutation && ST.hasVInstructions()) {
DAG = DAG ? DAG : createGenericSchedLive(C);
DAG = DAG ? DAG : createSchedLive(C);
DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
}
return DAG;
Expand All @@ -319,7 +319,7 @@ ScheduleDAGInstrs *
RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGMI *DAG = nullptr;
if (EnablePostMISchedLoadStoreClustering) {
DAG = createGenericSchedPostRA(C);
DAG = createSchedPostRA(C);
DAG->addMutation(createLoadClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
DAG->addMutation(createStoreClusterDAGMutation(
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -209,8 +209,7 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {

ScheduleDAGInstrs *
SystemZTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
return new ScheduleDAGMI(C, std::make_unique<SystemZPostRASchedStrategy>(C),
/*RemoveKillFlags=*/true);
return createSchedPostRA<SystemZPostRASchedStrategy>(C);
}

namespace {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86TargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -378,14 +378,14 @@ void X86TargetMachine::reset() { SubtargetMap.clear(); }

ScheduleDAGInstrs *
X86TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
ScheduleDAGMILive *DAG = createSchedLive(C);
DAG->addMutation(createX86MacroFusionDAGMutation());
return DAG;
}

ScheduleDAGInstrs *
X86TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
ScheduleDAGMI *DAG = createSchedPostRA(C);
DAG->addMutation(createX86MacroFusionDAGMutation());
return DAG;
}
Expand Down
Loading