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Merged
merged 1 commit into from
May 29, 2025
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AMDGPU: Regenerate test checks #141984

merged 1 commit into from
May 29, 2025

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@arsenm arsenm commented May 29, 2025

Update to new update_test_checks output

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arsenm commented May 29, 2025 •
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llvmbot commented May 29, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Update to new update_test_checks output

Patch is 40.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/141984.diff

1 Files Affected:

  • (modified) llvm/test/CodeGen/AMDGPU/fract-match.ll (+181-181)
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index d957ba93e4fb3..4307b79bf2c3b 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 
 ; Test with buggy fract, shouldn't match
 ; RUN: opt -S -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck -check-prefixes=IR,GFX6-IR %s
@@ -24,9 +24,9 @@
 ; floor. We can fold in the nan check into the instruction, but the
 ; inf check must remain.
 define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(none) %ip) {
-; GFX6-IR-LABEL: define float @safe_math_fract_f32
-; GFX6-IR-SAME: (float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0:[0-9]+]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @safe_math_fract_f32(
+; GFX6-IR-SAME: float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0:[0-9]+]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -38,9 +38,9 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
 ; GFX6-IR-NEXT:    store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
 ; GFX6-IR-NEXT:    ret float [[COND6]]
 ;
-; IR-FRACT-LABEL: define float @safe_math_fract_f32
-; IR-FRACT-SAME: (float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0:[0-9]+]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @safe_math_fract_f32(
+; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0:[0-9]+]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-FRACT-NEXT:    [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
@@ -135,9 +135,9 @@ entry:
 }
 
 define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeonly captures(none) %ip) {
-; GFX6-IR-LABEL: define float @safe_math_fract_f32_noinf_check
-; GFX6-IR-SAME: (float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @safe_math_fract_f32_noinf_check(
+; GFX6-IR-SAME: float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -146,9 +146,9 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeon
 ; GFX6-IR-NEXT:    store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
 ; GFX6-IR-NEXT:    ret float [[COND]]
 ;
-; IR-FRACT-LABEL: define float @safe_math_fract_f32_noinf_check
-; IR-FRACT-SAME: (float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @safe_math_fract_f32_noinf_check(
+; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-FRACT-NEXT:    [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
@@ -223,9 +223,9 @@ entry:
 
 ; Cannot match fract without a nan check or no-nans.
 define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(none) %ip) {
-; IR-LABEL: define float @no_nan_check_math_fract_f32
-; IR-SAME: (float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0:[0-9]+]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @no_nan_check_math_fract_f32(
+; IR-SAME: float [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0:[0-9]+]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -322,17 +322,17 @@ entry:
 }
 
 define float @basic_fract_f32_nonans(float nofpclass(nan) %x) {
-; GFX6-IR-LABEL: define float @basic_fract_f32_nonans
-; GFX6-IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @basic_fract_f32_nonans(
+; GFX6-IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
 ; GFX6-IR-NEXT:    ret float [[MIN]]
 ;
-; IR-FRACT-LABEL: define float @basic_fract_f32_nonans
-; IR-FRACT-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @basic_fract_f32_nonans(
+; IR-FRACT-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    ret float [[MIN]]
 ;
@@ -379,9 +379,9 @@ entry:
 }
 
 define float @basic_fract_f32_flags_minnum(float %x) {
-; IR-LABEL: define float @basic_fract_f32_flags_minnum
-; IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @basic_fract_f32_flags_minnum(
+; IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call nsz float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -440,17 +440,17 @@ entry:
 }
 
 define float @basic_fract_f32_flags_fsub(float nofpclass(nan) %x) {
-; GFX6-IR-LABEL: define float @basic_fract_f32_flags_fsub
-; GFX6-IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @basic_fract_f32_flags_fsub(
+; GFX6-IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub nsz float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
 ; GFX6-IR-NEXT:    ret float [[MIN]]
 ;
-; IR-FRACT-LABEL: define float @basic_fract_f32_flags_fsub
-; IR-FRACT-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @basic_fract_f32_flags_fsub(
+; IR-FRACT-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    ret float [[MIN]]
 ;
@@ -497,17 +497,17 @@ entry:
 }
 
 define <2 x float> @basic_fract_v2f32_nonans(<2 x float> nofpclass(nan) %x) {
-; GFX6-IR-LABEL: define <2 x float> @basic_fract_v2f32_nonans
-; GFX6-IR-SAME: (<2 x float> nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define <2 x float> @basic_fract_v2f32_nonans(
+; GFX6-IR-SAME: <2 x float> nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call <2 x float> @llvm.floor.v2f32(<2 x float> [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub <2 x float> [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call <2 x float> @llvm.minnum.v2f32(<2 x float> [[SUB]], <2 x float> splat (float 0x3FEFFFFFE0000000))
 ; GFX6-IR-NEXT:    ret <2 x float> [[MIN]]
 ;
-; IR-FRACT-LABEL: define <2 x float> @basic_fract_v2f32_nonans
-; IR-FRACT-SAME: (<2 x float> nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define <2 x float> @basic_fract_v2f32_nonans(
+; IR-FRACT-SAME: <2 x float> nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[TMP0:%.*]] = extractelement <2 x float> [[X]], i64 0
 ; IR-FRACT-NEXT:    [[TMP1:%.*]] = extractelement <2 x float> [[X]], i64 1
 ; IR-FRACT-NEXT:    [[TMP2:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[TMP0]])
@@ -566,18 +566,18 @@ entry:
 }
 
 define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr addrspace(1) %ptr) {
-; GFX6-IR-LABEL: define float @basic_fract_f32_multi_use_fsub_nonans
-; GFX6-IR-SAME: (float nofpclass(nan) [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @basic_fract_f32_multi_use_fsub_nonans(
+; GFX6-IR-SAME: float nofpclass(nan) [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
 ; GFX6-IR-NEXT:    store float [[SUB]], ptr addrspace(1) [[PTR]], align 4
 ; GFX6-IR-NEXT:    ret float [[MIN]]
 ;
-; IR-FRACT-LABEL: define float @basic_fract_f32_multi_use_fsub_nonans
-; IR-FRACT-SAME: (float nofpclass(nan) [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @basic_fract_f32_multi_use_fsub_nonans(
+; IR-FRACT-SAME: float nofpclass(nan) [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-FRACT-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-FRACT-NEXT:    [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
@@ -654,17 +654,17 @@ entry:
 }
 
 define float @nnan_minnum_fract_f32(float %x) {
-; GFX6-IR-LABEL: define float @nnan_minnum_fract_f32
-; GFX6-IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @nnan_minnum_fract_f32(
+; GFX6-IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call nnan float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
 ; GFX6-IR-NEXT:    ret float [[MIN]]
 ;
-; IR-FRACT-LABEL: define float @nnan_minnum_fract_f32
-; IR-FRACT-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @nnan_minnum_fract_f32(
+; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    ret float [[MIN]]
 ;
@@ -713,9 +713,9 @@ entry:
 ; TODO: Could match if we checked isKnownNeverNaN on the minnum src
 ; instead of the pattern input source.
 define float @nnan_fsub_fract_f32(float %x) {
-; IR-LABEL: define float @nnan_fsub_fract_f32
-; IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @nnan_fsub_fract_f32(
+; IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub nnan float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -774,9 +774,9 @@ entry:
 }
 
 define float @nnan_floor_fract_f32(float %x) {
-; IR-LABEL: define float @nnan_floor_fract_f32
-; IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @nnan_floor_fract_f32(
+; IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call nnan float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -835,17 +835,17 @@ entry:
 }
 
 define float @nnan_src_fract_f32(float nofpclass(nan) %x) {
-; GFX6-IR-LABEL: define float @nnan_src_fract_f32
-; GFX6-IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @nnan_src_fract_f32(
+; GFX6-IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
 ; GFX6-IR-NEXT:    ret float [[MIN]]
 ;
-; IR-FRACT-LABEL: define float @nnan_src_fract_f32
-; IR-FRACT-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @nnan_src_fract_f32(
+; IR-FRACT-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    ret float [[MIN]]
 ;
@@ -893,9 +893,9 @@ entry:
 
 ; Negative test
 define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) {
-; IR-LABEL: define float @not_fract_f32_wrong_const
-; IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @not_fract_f32_wrong_const(
+; IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFC0000000)
@@ -955,9 +955,9 @@ entry:
 
 ; Negative test
 define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) {
-; IR-LABEL: define float @not_fract_f32_swapped_fsub
-; IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @not_fract_f32_swapped_fsub(
+; IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[FLOOR]], [[X]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1017,9 +1017,9 @@ entry:
 
 ; Negative test
 define float @not_fract_f32_not_floor(float nofpclass(nan) %x) {
-; IR-LABEL: define float @not_fract_f32_not_floor
-; IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @not_fract_f32_not_floor(
+; IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.trunc.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1079,9 +1079,9 @@ entry:
 
 ; Negative test
 define float @not_fract_f32_different_floor(float %x, float %y) {
-; IR-LABEL: define float @not_fract_f32_different_floor
-; IR-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @not_fract_f32_different_floor(
+; IR-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[Y]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1141,9 +1141,9 @@ entry:
 
 ; Negative test
 define float @not_fract_f32_maxnum(float nofpclass(nan) %x) {
-; IR-LABEL: define float @not_fract_f32_maxnum
-; IR-SAME: (float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @not_fract_f32_maxnum(
+; IR-SAME: float nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.maxnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1202,9 +1202,9 @@ entry:
 }
 
 define float @fcmp_uno_check_is_nan_f32(float %x) {
-; IR-LABEL: define float @fcmp_uno_check_is_nan_f32
-; IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @fcmp_uno_check_is_nan_f32(
+; IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1236,9 +1236,9 @@ entry:
 
 ; No inf check
 define float @select_nan_fract_f32(float %x) {
-; GFX6-IR-LABEL: define float @select_nan_fract_f32
-; GFX6-IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @select_nan_fract_f32(
+; GFX6-IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1246,9 +1246,9 @@ define float @select_nan_fract_f32(float %x) {
 ; GFX6-IR-NEXT:    [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
 ; GFX6-IR-NEXT:    ret float [[COND]]
 ;
-; IR-FRACT-LABEL: define float @select_nan_fract_f32
-; IR-FRACT-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @select_nan_fract_f32(
+; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    ret float [[COND]]
 ;
@@ -1299,9 +1299,9 @@ entry:
 }
 
 define float @commuted_select_nan_fract_f32(float %x) {
-; GFX6-IR-LABEL: define float @commuted_select_nan_fract_f32
-; GFX6-IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; GFX6-IR-NEXT:  entry:
+; GFX6-IR-LABEL: define float @commuted_select_nan_fract_f32(
+; GFX6-IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; GFX6-IR-NEXT:  [[ENTRY:.*:]]
 ; GFX6-IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; GFX6-IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; GFX6-IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1309,9 +1309,9 @@ define float @commuted_select_nan_fract_f32(float %x) {
 ; GFX6-IR-NEXT:    [[COND:%.*]] = select i1 [[UNO]], float [[MIN]], float [[X]]
 ; GFX6-IR-NEXT:    ret float [[COND]]
 ;
-; IR-FRACT-LABEL: define float @commuted_select_nan_fract_f32
-; IR-FRACT-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-FRACT-NEXT:  entry:
+; IR-FRACT-LABEL: define float @commuted_select_nan_fract_f32(
+; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-FRACT-NEXT:  [[ENTRY:.*:]]
 ; IR-FRACT-NEXT:    [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
 ; IR-FRACT-NEXT:    ret float [[COND]]
 ;
@@ -1362,9 +1362,9 @@ entry:
 }
 
 define float @wrong_commuted_nan_select_f32(float %x) {
-; IR-LABEL: define float @wrong_commuted_nan_select_f32
-; IR-SAME: (float [[X:%.*]]) #[[ATTR0]] {
-; IR-NEXT:  entry:
+; IR-LABEL: define float @wrong_commuted_nan_select_f32(
+; IR-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; IR-NEXT:  [[ENTRY:.*:]]
 ; IR-NEXT:    [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
 ; IR-NEXT:    [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
 ; IR-NEXT:    [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
@@ -1440,25 +1440,25 @@ entry:
 }
 
 define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
-...
[truncated]

@arsenm arsenm marked this pull request as ready for review May 29, 2025 17:05
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arsenm commented May 29, 2025 •
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  • May 29, 7:50 PM UTC: A user started a stack merge that includes this pull request via Graphite.
  • May 29, 7:52 PM UTC: Graphite rebased this pull request as part of a merge.
  • May 29, 7:54 PM UTC: @arsenm merged this pull request with Graphite.

@arsenm
AMDGPU: Regenerate test checks
56292a5 
Update to new update_test_checks output
@arsenm arsenm force-pushed the users/arsenm/amdgpu/regenerate-baseline-checks-fract-match branch from c8c377f to 56292a5 Compare May 29, 2025 19:51
@arsenm arsenm merged commit b3660e4 into main May 29, 2025
6 of 9 checks passed
@arsenm arsenm deleted the users/arsenm/amdgpu/regenerate-baseline-checks-fract-match branch May 29, 2025 19:54
svkeerthy pushed a commit that referenced this pull request May 29, 2025
@arsenm @svkeerthy
AMDGPU: Regenerate test checks (#141984)
4676efe 
Update to new update_test_checks output
google-yfyang pushed a commit to google-yfyang/llvm-project that referenced this pull request May 29, 2025
@arsenm @google-yfyang
AMDGPU: Regenerate test checks (llvm#141984)
f27b1e4 
Update to new update_test_checks output
sivan-shani pushed a commit to sivan-shani/llvm-project that referenced this pull request Jun 3, 2025
@arsenm @sivan-shani
AMDGPU: Regenerate test checks (llvm#141984)
4b163c7 
Update to new update_test_checks output
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